Contributors
A
Engineering Tracks Low Power Classes as extension to UVM Package Library
Networking Reception Two-level Hierarchical Cluster-Node Scheduling for Heterogeneous Datacenters
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
Engineering Track Poster Time Interleaving of Analog to Digital Converters Calibration Techniques
Networking Reception HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Engineering Tracks Intelligent Floorplanning (IFP)
Engineering Track Poster Formal Verification of Deep Neural Networks in Hardware
Engineering Track Poster Learnings from RDC Sign-Off on Low Power SoC
Networking Reception Accelerating Data Analytics near Memory: A k-NN Search Case Study
Special Session (Research) Challenges and Opportunities for In-memory Compute
Networking Reception Energy Profiling of USB DNN Accelerators
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Networking Reception Leveraging Layout-based Effects for Locking Analog ICs
Research Panel Automating Analog Layout - Has the time finally come?
Engineering Track Poster Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
Research Manuscript Future Unleashed: Beyond-CMOS Meets the Real World
Research Manuscript Improving LUT-Based Optimization for ASIC
Networking Reception System-Level Design and Target Agnostic High-Level Optimizations for HLS
Networking Reception On the (in)security of Memory Protection Units
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript Fast and Scalable Human Pose Estimation using mmWave Point Cloud
Research Manuscript Do Not Forget the Software: Bare Metal Neural Acceleration is no fun without it.
Engineering Track Poster Shift Left Performance Verification using Formal Methods for ML ASICs
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Research Manuscript Resist Faults and Make Memories Smarter
Research Manuscript NAX: Neural Architecture and Memristive Xbar based Accelerator Co-design
Research Manuscript Response-Time Analysis for Deadline-Based Scheduling of ROS2
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Engineering Track Poster Low Power Verification Challenges of Hierarchical UPF in Discrete Graphics SoC Design
Networking Reception RFR: An STT-MRAM Cache Management Scheme for Retention Failure Reduction
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Networking Reception A Coq Framework for More Trustworthy DRAM Controllers
Research Manuscript Bringing Source-Level Debugging Frameworks to Hardware Generators
Research Manuscript Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization
Research Manuscript Apple vs. EMA: Electromagnetic Side Channel Attacks on Apple CoreCrypto
Engineering Tracks NOVEL DESIGN OF REAL TIME CLOCK MACRO FOR ADVANCED FINFET TECHNOLOGY NODES
B
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Networking Reception Bounded BaT: Bounded Backup Time for Intermittent Power Devices
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Engineering Track Poster Learnings from RDC Sign-Off on Low Power SoC
Engineering Track Poster Clustering Characterization Condition for Multi-bit Cell
Engineering Track Poster Static Timing and Power Analysis with Process Space Exploration
Engineering Track Poster PostMask functional ECO Implementation flow using Programmable cells
Engineering Track Poster Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Research Manuscript GTuner: Tuning DNN Computations on GPU via Graph Attention Network
Research Manuscript Automated Accelerator Optimization Aided by Graph Neural Networks
Special Session (Research) Democratizing Customized Computing with Automated Accelerator Synthesis
Engineering Tracks ML for Verification: Does it Work or Doesn’t It?
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
Engineering Track Poster Efficient Low Power Isolation Handling for Pre-Silicon Emulation
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Research Manuscript PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
Networking Reception Endurance-Aware Deep Neural Network Real-Time Scheduling on ReRAM Accelerators
Research Panel What is the Future for Open-Source EDA?
Engineering Track Poster Efficient Low Power Isolation Handling for Pre-Silicon Emulation
Engineering Tracks Digital Twin Reimagined - One Model To Rule Them All ?
Engineering Tracks ML for Verification: Does it Work or Doesn’t It?
Networking Reception Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis
Engineering Track Poster Path-Finding Through Variability-Aware DTCO-Flow
Engineering Tracks I/O Constraints Optimization
Networking Reception Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Networking Reception Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
Networking Reception A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Networking Reception On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Engineering Tracks ML for Verification: Does it Work or Doesn’t It?
Special Session (Research) ADA, the Center for Applications Driving Architectures: Accomplishments and Vision Forward
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Engineering Track Poster Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Networking Reception AutoPilot: Compute Design Automation for Autonomous Drones
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Networking Reception A Custom Macro Suite for Optimization of Neuromorphic TNN Designs in CMOS
Engineering Tracks Pushing Boundaries - Challenges for Next-Generation Chip Design
Research Manuscript Hot Application and Cool Automation for Quantum Computing
Research Manuscript VIPR-PCB: A Machine Learning based Golden-Free PCB Assurance Framework
Engineering Track Poster Building a Robust Power Grid for Multi Million SoC using RedHawk-SC Early PG Grid Analysis
Research Manuscript Optimizing Quantum Circuit Synthesis for Permutations using Recursive Methods
Engineering Track Poster CDC Signoff Flow with DFT Logic
Networking Reception TrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
Research Manuscript Cool Interconnects for Cool Accelerators on Top of Congestion Free Place & Route
Special Session (Research) Quantum Algorithm Design: A new tool for the design automation of quantum computing circuits
Networking Reception System-Level Design and Target Agnostic High-Level Optimizations for HLS
Research Manuscript Domain-Specific PIM Accelerators from Client to Cloud
Networking Reception Circumventing Machine Learning-Based Attacks to Logic Locking
Engineering Tracks Verifying Register Maps with JasperGold: How Formal compares to UVM
Networking Reception Modular software for real-time quantum control systems
Engineering Track Poster Generation And Selection Of Universally Routable Via Mesh Specifications
Engineering Track Poster Solving Antenna Errors for Hierarchical Designs
Engineering Track Poster TCP/IP Hardware Stack Design and Verification Challenges
Networking Reception A Coq Framework for More Trustworthy DRAM Controllers
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Networking Reception Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Research Manuscript A Joint Management Middleware to Improve Training Performance of Deep Recommendation Systems with SSDs
Networking Reception AutoPilot: Compute Design Automation for Autonomous Drones
Special Session (Research) Co-designing algorithms and hardware for efficient TinyML
Networking Reception Modular software for real-time quantum control systems
Engineering Track Poster Static Timing and Power Analysis with Process Space Exploration
Networking Reception Instant Data Sanitization on Multi-Level-Cell NAND Flash Memory
Networking Reception FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Research Manuscript Equivalence Checking Paradigms in Quantum Circuit Design: A Case Study
Research Manuscript Handling Non-Unitaries in Quantum Circuit Equivalence Checking
Special Session (Research) The Basis of Design Tools for Quantum Computing: Arrays, Decision Diagrams, Tensor Networks, and more
Research Panel Automating Analog Layout - Has the time finally come?
C
Engineering Tracks I/O Constraints Optimization
Engineering Track Poster Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Networking Reception A method for hierarchical, transistor-level circuit simulation
Research Manuscript AL-PA: Cross-Device Profiled Side-Channel Attack using Adversarial Learning
Networking Reception Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Networking Reception A Built-In Adaptive NDA for High-Level Language Acceleration
Networking Reception Aggressive Performance Improvement on PIM Devices by Adopting Hugepages
Networking Reception Performance Impact of Inter-PIM Communication
Networking Reception Vector In Memory Architecture for simple and high efficiency computing
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Engineering Tracks Automatic Checkpoint Support in the Device Modeling Language (DML)
Networking Reception System-Level Design and Target Agnostic High-Level Optimizations for HLS
Engineering Tracks Timing Analytics and Reporting: From Design Start to Finish
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Engineering Tracks Machine Learning and EDA: The Productivity Cycle
Research Manuscript Hot Application and Cool Automation for Quantum Computing
Networking Reception Attacking the TimingCamouflage+ Algorithm
Research Manuscript NAX: Neural Architecture and Memristive Xbar based Accelerator Co-design
Engineering Track Poster Shift Left DFT Sign-off Methodology for Edge AI Processor
Research Manuscript VIPR-PCB: A Machine Learning based Golden-Free PCB Assurance Framework
Research Manuscript Fast and Fiducius: Achieving Efficient Autonomy with Confidence
Networking Reception Automation of Functional Safety and Security Methods for Design and Verification
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
Research Manuscript Keep moving up and looking sideways with verification boosters!
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript Rethinking Key-Value Store for Byte-Addressable Optane Persistent Memory
Research Manuscript SSD: Storage Supremacy for lifelong Data
Engineering Tracks New Directions in Silicon Solutions
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript HCG: Optimizing Embedded Code Generation of Simulink with SIMD Instruction Synthesis
Research Manuscript Precise and Scalable Shared Cache Contention Analysis for WCET Estimation
Networking Reception MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits
Research Manuscript CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints
Networking Reception Subgraph Matching Based Reference Placement for PCB Designs
Engineering Tracks SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Networking Reception MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Special Session (Research) Using Logic to Understand Learning
Research Manuscript Hardware security potpourri: logic locking, hardware Trojans, and memory attacks
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Networking Reception Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Engineering Track Poster AI assisted smart analysis (AISA) for system level issue localization in post silicon validation
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Networking Reception ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript Optimizing Quantum Circuit Synthesis for Permutations using Recursive Methods
Networking Reception Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
Special Session (Research) ScaleHLS: A Scalable High-Level Synthesis Framework on MLIR
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Research Manuscript GaBAN: A Generic and Flexibly Programmable Vector Neuro-processor on FPGA
Engineering Track Poster Design Timing Effects of Layer-to-Layer Interconnect Skew
Research Manuscript CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs
Research Manuscript High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints
Networking Reception Subgraph Matching Based Reference Placement for PCB Designs
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Engineering Track Poster A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Research Manuscript libcrpm: Improving the Checkpoint Performance of NVM
Research Manuscript HIMap: A Heuristic and Iterative Logic Synthesis Approach
Research Manuscript TAAS: A Timing-Aware Analytical Strategy for AQFP-Capable Placement Automation
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Networking Reception An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Engineering Track Poster XMAS: An Efficient Customizable Flow for Crossbarred-Memristor Architecture Search
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Networking Reception Flexible Chip Placement via Reinforcement Learning
Networking Reception Modular software for real-time quantum control systems
Research Manuscript A Fast Parameter Tuning Framework via Transfer Learning and Multi-objective Bayesian Optimization
Networking Reception Aging-aware Critical Path Selection via Graph Attentional Networks
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript Be Water: Adaptive AI for Dynamic Systems
Networking Reception Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
Networking Reception MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript DA PUF: Dual-State Analog PUF
Research Manuscript Novel approaches for scaling routing and DFM challenges
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Engineering Track Poster A Comprehensive Electromagnetic Analysis for Transmission Line in High-Speed AMS Design
Networking Reception Enabling Versatile Power Management for AIoT Devices
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Research Manuscript A scalable symbolic simulation tool for low power embedded systems
Networking Reception RFR: An STT-MRAM Cache Management Scheme for Retention Failure Reduction
Networking Reception MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Engineering Tracks Low Power Classes as extension to UVM Package Library
Networking Reception Efficient Timing Propagation with Simultaneous Structural and Pipeline Parallelisms
Engineering Track Poster Efficient Custom Logic P&R Flow using Virtual Hierarchy
Networking Reception Thermal-Aware Drone Battery Management
Engineering Track Poster Fast Design Space Exploration using RTL Architect for DRAM Designs
Research Manuscript Bipolar Vector Classifier for Fault-tolerant Deep Neural Networks
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript CarM: Hierarchical Episodic Memory for Continual Learning
Networking Reception Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Track Poster Efficient Custom Logic P&R Flow using Virtual Hierarchy
Research Manuscript NN-LUT: Neural Approximation of Non-Linear Operations for Efficient Transformer Inference
Research Manuscript New Normal for In-Memory Computing: Novel Circuits and Systems
Engineering Tracks Extracting Source of Unknown Values in Transistor-level Logic Simulation
Engineering Track Poster Fast Design Space Exploration using RTL Architect for DRAM Designs
Engineering Track Poster New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster Cell EM aware Design Optimization
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Track Poster Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Research Manuscript RobustQNN: Noise-Aware Training for Robust Quantum Neural Networks
Engineering Track Poster SDR (Simulation-Driven Routing): A Solution to Get Electromigration Compliant Routing
Networking Reception Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
Networking Reception Flexible Chip Placement via Reinforcement Learning
Networking Reception RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Special Session (Research) Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
Networking Reception Equivalence Checking for Agile Hardware Design
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Manuscript Designing ML-Resilient Locking at Register-Transfer Level
Research Manuscript Automated Accelerator Optimization Aided by Graph Neural Networks
Special Session (Research) Democratizing Customized Computing with Automated Accelerator Synthesis
Networking Reception Vector In Memory Architecture for simple and high efficiency computing
Engineering Track Poster A unified IP QA methodology to improve validation coverage and throughput
Engineering Tracks The Hardware/Software Nexus in Chip Design
Networking Reception HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Research Manuscript Improving Compute In-Memory ECC Reliability with Successive Correction
Engineering Tracks Encryption Interoperability with IEEE 1735
Networking Reception On the (in)security of Memory Protection Units
Research Manuscript VIPR-PCB: A Machine Learning based Golden-Free PCB Assurance Framework
Networking Reception par-gem5: Parallelizing gem5’s Atomic Mode
Networking Reception System-Level Design and Target Agnostic High-Level Optimizations for HLS
D
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Research Manuscript Heuristic Adaptability to Input Dynamics for SpMM on GPUs*
Engineering Tracks Maximize GPGPU performance-per-watt across real scenarios with 10x efficient power solution
Engineering Track Poster Power solution to maximize performance-per-watt for GPGPU
Networking Reception Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Research Manuscript NobLSM: An LSM-tree with Non-blocking Writes for SSDs
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Networking Reception A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Engineering Tracks The Hardware/Software Nexus in Chip Design
Research Manuscript Machine Learning for Resource Management: From Edge to Cloud
Engineering Track Poster Shift Left DFT Sign-off Methodology for Edge AI Processor
Special Session (Research) A Systems driven approach to Semiconductor Research and Innovation
Research Panel Cryogenic Computing, Super Cool or Not?
Networking Reception RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Networking Reception Neural Network Layer Assignment for Distributed Inference via Integer Programming
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript Improving Compute In-Memory ECC Reliability with Successive Correction
Engineering Tracks Timing Analytics and Reporting: From Design Start to Finish
Engineering Track Poster Solving Antenna Errors for Hierarchical Designs
DAC Pavilion Panel How Robust is Your Hardware Security Program?
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Networking Reception PRIME: A PRocessing In Memory HardwareEmulation Framework
Research Manuscript Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing*
Engineering Tracks Pushing Boundaries - Challenges for Next-Generation Chip Design
Networking Reception A Secure Design Methodology to Prevent Targeted Trojan Insertion During Fabrication
Engineering Track Poster Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Engineering Track Poster Design Timing Effects of Layer-to-Layer Interconnect Skew
Engineering Track Poster Static Timing and Power Analysis with Process Space Exploration
Research Manuscript DA PUF: Dual-State Analog PUF
Engineering Track Poster A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Research Manuscript On-Chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks
Research Manuscript RobustQNN: Noise-Aware Training for Robust Quantum Neural Networks
Research Manuscript Heuristic Adaptability to Input Dynamics for SpMM on GPUs*
Research Manuscript Robust Quantum Computing: Wild Goose Chase?
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Research Manuscript Floorplanning with Graph Attention
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Engineering Tracks Routing Congestion Prediction with Machine Learning in Physical Synthesis
Research Manuscript HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression
Networking Reception RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Research Manuscript Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Networking Reception Qualification of Metamorphic Relations for System Level AMS Models using Data Flow Coverage
Research Manuscript Robust Quantum Computing: Wild Goose Chase?
Research Manuscript Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Engineering Track Poster Low Power Verification Challenges of Hierarchical UPF in Discrete Graphics SoC Design
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Research Manuscript So You Want a Better Design? Go with Faster Timing and Lower Power Please!
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Networking Reception Circumventing Machine Learning-Based Attacks to Logic Locking
Engineering Track Poster Mitigation of Soft-Errors in Storage Elements through Layout and Circuit Design Techniques
Research Manuscript Repeal Murphy's Law: Avoid Errors
E
Networking Reception HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Networking Reception Bridger: Fast Token Delivery in Elastic Circuits
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Engineering Track Poster Clock Scripting for Reliable Design Flow
Engineering Track Poster AI assisted smart analysis (AISA) for system level issue localization in post silicon validation
Engineering Track Poster TCP/IP Hardware Stack Design and Verification Challenges
Networking Reception Aggressive Performance Improvement on PIM Devices by Adopting Hugepages
Networking Reception Performance Impact of Inter-PIM Communication
Engineering Tracks Automatic Checkpoint Support in the Device Modeling Language (DML)
Engineering Tracks The Hardware/Software Nexus in Chip Design
Networking Reception Tackling Resource Utilization in DNN Accelerators
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Engineering Track Poster Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
Engineering Track Poster Porting software to hardware using XLS/DSLX
Networking Reception FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter
Research Manuscript PATH: Evaluation of Boolean Logic using Path-based In-Memory Computing
Research Manuscript Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization
F
Engineering Track Poster Dealing with Silicon Aging in Digital Implementation using Library Metrics
Networking Reception ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Engineering Track Poster A Comprehensive Electromagnetic Analysis for Transmission Line in High-Speed AMS Design
Networking Reception Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Networking Reception A Built-In Adaptive NDA for High-Level Language Acceleration
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
Special Session (Research) Secure by Construction: Addressing Security Vulnerabilities Introduced During High-level Synthesis
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Networking Reception AutoPilot: Compute Design Automation for Autonomous Drones
Networking Reception Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Engineering Track Poster Machine Learning Techniques for PDK Development Efficiency
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Engineering Tracks Characterization Challenges in System Level IO Interface
Networking Reception Leveraging Layout-based Effects for Locking Analog ICs
Engineering Tracks Refining Tapeout: Automation for Simplicity and Accuracy
Engineering Track Poster Automated DCAP and filler cell insertion with embedded Design for Inspection (DFI) Sensors
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Engineering Track Poster A unified IP QA methodology to improve validation coverage and throughput
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript Xplace: An Extremely Fast and Extensible Global Placement Framework
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Research Manuscript Accurate Timing Prediction at Placement Stage with Look-Ahead RC Network
Special Session (Research) Automating Hardware Security Property Generation
DAC Pavilion Panel How Robust is Your Hardware Security Program?
G
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Manuscript Improving LUT-Based Optimization for ASIC
Research Manuscript MetaZip: A High-throughput and Efficient Accelerator for DEFLATE
Networking Reception Aging-aware Critical Path Selection via Graph Attentional Networks
Engineering Tracks Characterization Challenges in System Level IO Interface
Special Session (Research) High-level design methods for hardware security: Is it the right choice?
Networking Reception Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
Engineering Tracks Timing Analytics and Reporting: From Design Start to Finish
Engineering Track Poster Library Analytics and Library Partitioning [LALP] for PPA Efficiency
Engineering Track Poster Diagnosis of Faults by Fault Simulation on PCIe
Networking Reception Automatic Generation of Cell Based structured CIM Macros
Networking Reception Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
Engineering Track Poster Library Analytics and Library Partitioning [LALP] for PPA Efficiency
Engineering Track Poster Diagnosis of Faults by Fault Simulation on PCIe
Networking Reception A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
Engineering Track Poster Formal based Automation Framework to Verify Coherent Connectivity of Multi-instance IPs
Engineering Track Poster Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement
Networking Reception Bounded BaT: Bounded Backup Time for Intermittent Power Devices
Research Manuscript DETERRENT: Detecting Trojans using Reinforcement Learning
Engineering Track Poster Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
Networking Reception On the (in)security of Memory Protection Units
Research Manuscript Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Research Manuscript Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Networking Reception Waveform-based Performance Analysis of RISC-V Processors
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Special Session (Research) The Basis of Design Tools for Quantum Computing: Arrays, Decision Diagrams, Tensor Networks, and more
Research Manuscript AL-PA: Cross-Device Profiled Side-Channel Attack using Adversarial Learning
Research Manuscript GEML: GNN-Based Efficient Mapping Method for Large Loop Applications on CGRA
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript On-Chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks
Research Manuscript RobustQNN: Noise-Aware Training for Robust Quantum Neural Networks
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript Optimizing Parallel PREM Compilation over Nested Loop Structures
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
Networking Reception Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Networking Reception Two-level Hierarchical Cluster-Node Scheduling for Heterogeneous Datacenters
Engineering Track Poster XMAS: An Efficient Customizable Flow for Crossbarred-Memristor Architecture Search
Networking Reception RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
Engineering Track Poster XMAS: An Efficient Customizable Flow for Crossbarred-Memristor Architecture Search
Networking Reception Bridger: Fast Token Delivery in Elastic Circuits
Engineering Track Poster Physically Unclonable Function Compliant with ISO/IEC 20897-1:2020
Research Manuscript CamSkyGate: Camouflaged Skyrmion Gates for Protecting ICs
Networking Reception Automation of Functional Safety and Security Methods for Design and Verification
Engineering Track Poster Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks VFopt: ML-Based Optimization Voltage/Frequency Exploration System
Research Manuscript Optimizing Quantum Circuit Placement via Machine Learning
Research Manuscript DETERRENT: Detecting Trojans using Reinforcement Learning
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
Research Manuscript Designing Critical Systems with Iterative Automated Safety Analysis
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Research Manuscript Accurate Timing Prediction at Placement Stage with Look-Ahead RC Network
Networking Reception Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Manuscript Response-Time Analysis for Deadline-Based Scheduling of ROS2
Research Manuscript Timing-Critical Design
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS
Research Manuscript Differentiable Timing Driven Global Placement
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Engineering Tracks I/O Constraints Optimization
Engineering Track Poster Efficient Low Power Isolation Handling for Pre-Silicon Emulation
H
Networking Reception Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Research Manuscript Apple vs. EMA: Electromagnetic Side Channel Attacks on Apple CoreCrypto
Research Manuscript Thinking Fast and Acting Smart: Accelerated and Intelligent IoT
Engineering Track Poster History based Physical Synthesis
Research Manuscript GEML: GNN-Based Efficient Mapping Method for Large Loop Applications on CGRA
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Engineering Track Poster Static Timing and Power Analysis with Process Space Exploration
Research Manuscript Solving Traveling Salesman Problems via a Parallel Fully Connected Ising Machine
Research Manuscript On-Chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks
Research Manuscript RobustQNN: Noise-Aware Training for Robust Quantum Neural Networks
Engineering Track Poster Efficient read/write turn-around policy of LPDDR5 memory controller
Engineering Tracks Digital Twin Reimagined - One Model To Rule Them All ?
Tutorial A Journey to SW/HW Co-design in Machine Learning: Fundamental, Advancement, and Application
Networking Reception Error Distribution Modeling for Behavior-level Approximate Computing
Research Manuscript H2H: Heterogeneous Model to Heterogeneous System Mapping with Computation and Communication Awareness
Research Manuscript High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
Networking Reception Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information
Research Manuscript So You Want a Better Design? Go with Faster Timing and Lower Power Please!
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Research Manuscript BlueSeer: AI-Driven Environment Detection via BLE Scans*
Networking Reception SoC Platform for Heterogeneous Multiple IP Core Evaluation
Engineering Track Poster DVD Diagnostics - Debugging Dynamic IR problems using Advanced Analytics
Networking Reception Subgraph Matching Based Reference Placement for PCB Designs
Research Manuscript Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception
Research Manuscript Novel Circuits for PIM
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
Research Manuscript A scalable symbolic simulation tool for low power embedded systems
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Engineering Track Poster Billion Instance Timing Sign-off
Networking Reception Fingerprinting Workloads for Reconfigurable Shared Accelerators
Networking Reception MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Networking Reception Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Engineering Track Poster Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Track Poster Static Timing and Power Analysis with Process Space Exploration
Engineering Track Poster Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks VFopt: ML-Based Optimization Voltage/Frequency Exploration System
Research Manuscript Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Special Session (Research) The Basis of Design Tools for Quantum Computing: Arrays, Decision Diagrams, Tensor Networks, and more
Engineering Tracks Design Considerations for Embedded at the Edge
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Networking Reception A Secure Design Methodology to Prevent Targeted Trojan Insertion During Fabrication
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Engineering Track Poster Workflow Automation for SoC Performance Verification
Research Manuscript Bringing Source-Level Debugging Frameworks to Hardware Generators
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Networking Reception Adaptive Sparsity-Aware Cloud Offloading for Edge DNN Inference
Networking Reception Enabling Versatile Power Management for AIoT Devices
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Networking Reception ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Networking Reception ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Networking Reception Flexible Chip Placement via Reinforcement Learning
Engineering Track Poster Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Track Poster Design Timing Effects of Layer-to-Layer Interconnect Skew
Research Manuscript Cost-Efficient Analog and Stochastic Computing Techniques for Deep Learning
Networking Reception ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript From machine learning to graphs: a new wave towards analog design
Research Manuscript H2H: Heterogeneous Model to Heterogeneous System Mapping with Computation and Communication Awareness
Research Manuscript Is Persistent Memory Real?
Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Research Manuscript ODHD: One-Class Hyperdimensional Computing for Outlier Detection
Research Manuscript SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators
Research Manuscript NobLSM: An LSM-tree with Non-blocking Writes for SSDs
Networking Reception Circumventing Machine Learning-Based Attacks to Logic Locking
Networking Reception Deep Reinforcement Learning Empowered Content Caching in Mobile Social Networks
Research Manuscript GuardNN: Secure Accelerator Architecture for Privacy-Preserving Deep Learning
Research Manuscript Scalable Crash Consistency for Secure Persistent Memory
Research Manuscript Heuristic Adaptability to Input Dynamics for SpMM on GPUs*
Research Manuscript Winograd Convolution: A Perspective from Fault Tolerance
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Networking Reception Efficient Timing Propagation with Simultaneous Structural and Pipeline Parallelisms
Engineering Track Poster A Comprehensive Electromagnetic Analysis for Transmission Line in High-Speed AMS Design
Research Manuscript DeepGate: Learning Neural Representations of Logic Gates*
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Engineering Track Poster Solving Antenna Errors for Hierarchical Designs
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript Pref-X: A Framework to Reveal Data Prefetching in Commercial In-Order Cores
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
Engineering Track Poster Design Timing Effects of Layer-to-Layer Interconnect Skew
Engineering Track Poster Minimize Power Consumption with A Novel Power ECO Flow
I
Special Session (Research) Secure by Construction: Addressing Security Vulnerabilities Introduced During High-level Synthesis
Networking Reception Bridger: Fast Token Delivery in Elastic Circuits
Networking Reception SoC Platform for Heterogeneous Multiple IP Core Evaluation
Networking Reception Graph Partitioning Approach for Fast Quantum Circuit Simulation
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Engineering Tracks Thermal-aware Power and Performance Simulator
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Research Manuscript Energy Efficient Data Search Design and Optimization Based on A Compact Ferroelectric FET Content Addressable Memory
Research Manuscript HDPG: Hyperdimensional Policy-based Reinforcement Learning for Continuous Control
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Engineering Track Poster Is Front-End Analog Design Automation an NP-type or simply a P-type problem ?
Networking Reception Energy Profiling of USB DNN Accelerators
Engineering Track Poster Overcoming IR Challenges for reticle sized ASIC in new architecture and advanced node
Research Panel Heterogeneous 3D or Monolithic 3D, Which Direction to Go?
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
J
Networking Reception A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Engineering Track Poster FSDB based Self-Gating technique for Power saving and FEV Verification approaches
Engineering Tracks NOVEL DESIGN OF REAL TIME CLOCK MACRO FOR ADVANCED FINFET TECHNOLOGY NODES
Networking Reception Addressing Ordering Woes of PCIe with Formal Verification
Engineering Track Poster Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
Engineering Tracks SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Networking Reception CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs
Special Session (Research) Prospects and Challenges for TinyML
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Networking Reception AutoPilot: Compute Design Automation for Autonomous Drones
Engineering Tracks Performance-driven Multi-bit Optimization Flow
Networking Reception A Model-Based Evaluation Framework for Battery Cell Balancing Techniques
Engineering Tracks Optimization of hot/cold separation algorithm computation for SSD
Networking Reception Energy Profiling of USB DNN Accelerators
Networking Reception RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Research Manuscript Optimizing Quantum Circuit Synthesis for Permutations using Recursive Methods
Special Session (Research) Quantum Information Science with Qiskit
Engineering Track Poster Concurrent Package + Interposer + Die IR Analysis using Ansys’ RedHawk-SC Electrothermal
Networking Reception Logic Locking Based Trojans: A Friend Turns Foe
Design on Cloud Training Google Cloud Training
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript CarM: Hierarchical Episodic Memory for Continual Learning
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Special Session (Research) ScaleHLS: A Scalable High-Level Synthesis Framework on MLIR
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Networking Reception FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter
Research Manuscript PATH: Evaluation of Boolean Logic using Path-based In-Memory Computing
Research Manuscript Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Research Manuscript Fast and Fiducius: Achieving Efficient Autonomy with Confidence
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
Engineering Track Poster Performance Optimization of Embedded FPGA
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Engineering Track Poster A Comprehensive Electromagnetic Analysis for Transmission Line in High-Speed AMS Design
Research Manuscript EMS: Efficient Memory Subsystem Synthesis for Spatial Accelerators
Research Manuscript A2-ILT: GPU Accelerated ILT with Spatial Attention Mechanism
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Networking Reception Improving GPU Performance via Coordinated Kernel Slicing and Multi CUDA Streaming
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Research Manuscript Efficient Bayesian Yield Analysis and Optimization with Active Learning
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Engineering Track Poster Overcoming IR Challenges for reticle sized ASIC in new architecture and advanced node
Engineering Track Poster Learnings from RDC Sign-Off on Low Power SoC
Research Manuscript Machine Learning for Resource Management: From Edge to Cloud
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Networking Reception par-gem5: Parallelizing gem5’s Atomic Mode
Engineering Tracks New Directions in Silicon Solutions
Networking Reception Bridger: Fast Token Delivery in Elastic Circuits
Engineering Track Poster Thermal Aware Memory Controller Design with Chip Package System Simulation
Research Manuscript Precise and Scalable Shared Cache Contention Analysis for WCET Estimation
Research Manuscript Floorplanning with Graph Attention
Special Session (Research) ScaleHLS: A Scalable High-Level Synthesis Framework on MLIR
Engineering Track Poster Workflow Automation for SoC Performance Verification
Engineering Track Poster ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Engineering Track Poster Cell EM aware Design Optimization
Special Session (Research) MRAM In - memory Computing Crossbar Array
Networking Reception SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
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Research Manuscript Silicon Validation of LUT-based Logic-Locked IP Cores
Networking Reception System-Level Design and Target Agnostic High-Level Optimizations for HLS
Research Panel Machine Learning for Electronic Design Automation: Irrational Exuberance or the Dawn of a Golden age
Special Session (Research) Shared Foundations for ML and EDA
Research Panel What is the Future for Open-Source EDA?
DAC Pavilion Panel Bespoke Silicon - Tailor-Made for Maximum Performance
Engineering Tracks IR drop fixing using Timing ECO integrated solution with IR Signoff tool
Engineering Tracks Timing Analytics and Reporting: From Design Start to Finish
Research Manuscript DETERRENT: Detecting Trojans using Reinforcement Learning
Engineering Track Poster Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
Engineering Tracks UPF Restructuring Flow Based On Power Promotion and Demotion Capabilities
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript A Near-Storage Framework for Boosted Data Preprocessing of Mass Spectrum Clustering
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Engineering Track Poster Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks VFopt: ML-Based Optimization Voltage/Frequency Exploration System
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Research Manuscript New Normal for In-Memory Computing: Novel Circuits and Systems
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster Cell EM aware Design Optimization
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Research Manuscript A Fast and Scalable Qubit-Mapping Method for NoisyIntermediate-Scale Quantum Computers
Networking Reception Graph Partitioning Approach for Fast Quantum Circuit Simulation
Engineering Tracks Power Aware Scan Structure Planner
Networking Reception FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Engineering Track Poster Path-Finding Through Variability-Aware DTCO-Flow
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Manuscript Designing ML-Resilient Locking at Register-Transfer Level
Special Session (Research) High-level design methods for hardware security: Is it the right choice?
Networking Reception Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Special Session (Research) Automating Hardware Security Property Generation
Engineering Track Poster Diagnosis of Faults by Fault Simulation on PCIe
Engineering Tracks Low Power Classes as extension to UVM Package Library
Engineering Track Poster Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Research Panel Cryogenic Computing, Super Cool or Not?
Networking Reception TrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
Engineering Tracks Routing Congestion Prediction with Machine Learning in Physical Synthesis
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript Designing Critical Systems with Iterative Automated Safety Analysis
Engineering Track Poster Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Panel Automating Analog Layout - Has the time finally come?
Research Manuscript GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
Research Manuscript DeepGate: Learning Neural Representations of Logic Gates*
Networking Reception Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Engineering Tracks I/O Constraints Optimization
Engineering Track Poster Fast Design Space Exploration using RTL Architect for DRAM Designs
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Engineering Tracks Optimization of hot/cold separation algorithm computation for SSD
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Engineering Track Poster Efficient Custom Logic P&R Flow using Virtual Hierarchy
Engineering Track Poster Workflow Automation for SoC Performance Verification
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster Fast Design Space Exploration using RTL Architect for DRAM Designs
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Engineering Track Poster Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Networking Reception Modular software for real-time quantum control systems
Networking Reception Modular software for real-time quantum control systems
Engineering Track Poster Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Tracks Extracting Source of Unknown Values in Transistor-level Logic Simulation
Engineering Track Poster ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Research Manuscript Iterate and Scale: Designing Stronger and Safer Embedded Systems
Engineering Track Poster Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
Engineering Tracks Design Rule Decision Methodology For Balancing Process Limit and Routability Improvement
Engineering Track Poster Minimize Power Consumption with A Novel Power ECO Flow
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Engineering Track Poster Minimize Power Consumption with A Novel Power ECO Flow
Engineering Tracks Learning-based Power Modeling for Versal AI Engine
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster Efficient read/write turn-around policy of LPDDR5 memory controller
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Engineering Track Poster Efficient read/write turn-around policy of LPDDR5 memory controller
Engineering Tracks Implementing QDI Design with Conventional Synchronous Design Flow: A Case of Long Distance Interconnect across Voltage Domain
Engineering Track Poster ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Engineering Track Poster Workflow Automation for SoC Performance Verification
Engineering Track Poster Fast Design Space Exploration using RTL Architect for DRAM Designs
Engineering Track Poster Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Networking Reception Constructing Large Buffers with HeterogeneousSTT-RAM Cells for DNN Accelerators
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Research Manuscript Thinking Fast and Acting Smart: Accelerated and Intelligent IoT
Engineering Tracks Machine Learning and EDA: The Productivity Cycle
DAC Pavilion Panel Bespoke Silicon - Tailor-Made for Maximum Performance
Networking Reception Waveform-based Performance Analysis of RISC-V Processors
Networking Reception Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Track Poster Thermal Aware Memory Controller Design with Chip Package System Simulation
Networking Reception Novel ML based Reconfigurable Macro Placement for SoC Design
Networking Reception DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms
Engineering Track Poster PostMask functional ECO Implementation flow using Programmable cells
Research Manuscript Adaptive Window-Based Sensor Attack Detection for Cyber-Physical Systems
Research Manuscript Can We Achieve a Secure, Robust, and Energy-efficient Cloud-Edge Continuum?
Engineering Track Poster Generation And Selection Of Universally Routable Via Mesh Specifications
Engineering Track Poster Solving Antenna Errors for Hierarchical Designs
Engineering Track Poster ROHD: The Rapid Open Hardware Development Framework
Research Manuscript Iterate and Scale: Designing Stronger and Safer Embedded Systems
Research Manuscript GEML: GNN-Based Efficient Mapping Method for Large Loop Applications on CGRA
Research Manuscript Preventing Brain Drain: How to Secure Next Generation AI
Networking Reception Energy Profiling of USB DNN Accelerators
Engineering Track Poster Thermal Aware Memory Controller Design with Chip Package System Simulation
Engineering Tracks Pathways to Realizations
Networking Reception AutoPilot: Compute Design Automation for Autonomous Drones
Research Manuscript Efficiency Attacks on Spiking Neural Networks
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Research Manuscript Exploiting Data Locality in Memory for ORAM to Reduce Memory Access Overheads
DAC Pavilion Panel How Robust is Your Hardware Security Program?
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Engineering Track Poster Ensuring Accurate Crosstalk Analysis using CCS-Noise Liberty Model
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Research Manuscript GNNIE: GNN Inference Engine with Load-balancing and Graph-specific Caching
Research Manuscript Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing*
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Networking Reception Modular software for real-time quantum control systems
Networking Reception PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
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Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Networking Reception MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Special Session (Research) Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
Engineering Track Poster Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Networking Reception Automatic Generation of Cell Based structured CIM Macros
Research Manuscript BlueSeer: AI-Driven Environment Detection via BLE Scans*
Engineering Tracks Refining Tapeout: Automation for Simplicity and Accuracy
Networking Reception Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
Research Manuscript Improving LUT-Based Optimization for ASIC
Engineering Track Poster Billion Instance Timing Sign-off
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Engineering Track Poster Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Engineering Tracks Performance-driven Multi-bit Optimization Flow
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Engineering Track Poster Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks VFopt: ML-Based Optimization Voltage/Frequency Exploration System
Engineering Track Poster Efficient Custom Logic P&R Flow using Virtual Hierarchy
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Track Poster Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
DAC Pavilion Panel Bespoke Silicon - Tailor-Made for Maximum Performance
Engineering Track Poster Efficient Custom Logic P&R Flow using Virtual Hierarchy
Engineering Track Poster Clustering Characterization Condition for Multi-bit Cell
Engineering Track Poster Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Engineering Track Poster ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Engineering Track Poster New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits
Research Manuscript CarM: Hierarchical Episodic Memory for Continual Learning
Engineering Track Poster Clustering Characterization Condition for Multi-bit Cell
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript Bipolar Vector Classifier for Fault-tolerant Deep Neural Networks
Engineering Track Poster ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Networking Reception Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information
Engineering Track Poster Dynamic CDC Verification with Enhanced Jitter Modeling in Synchronizers
Networking Reception Thermal-Aware Drone Battery Management
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Networking Reception Addressing Ordering Woes of PCIe with Formal Verification
Networking Reception PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory
Research Manuscript Designing ML-Resilient Locking at Register-Transfer Level
Engineering Tracks Rapid Embedded Software Verification Through Hardware-Accelerated, Parallel SystemC TLM Simulation - A RISC-V Example
Networking Reception X-on-X Simulation: Distributed Parallel SystemC TLM Virtual Platforms for Heterogeneous Systems
Networking Reception par-gem5: Parallelizing gem5’s Atomic Mode
Engineering Track Poster History based Physical Synthesis
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Research Manuscript InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs
Research Manuscript Optimizing Neural Network Hardware: Sparsity, Reuse and System
Networking Reception Enabling Versatile Power Management for AIoT Devices
Research Manuscript SS-LRU: A Smart Segmented LRU Caching for Storage System
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript TAAS: A Timing-Aware Analytical Strategy for AQFP-Capable Placement Automation
Research Manuscript InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Networking Reception ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript GLite: A Fast and Efficient Automatic Graph-Level Optimizer for Large-Scale DNNs
Networking Reception Improving GPU Performance via Coordinated Kernel Slicing and Multi CUDA Streaming
Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Research Manuscript DeepGate: Learning Neural Representations of Logic Gates*
Research Manuscript CamSkyGate: Camouflaged Skyrmion Gates for Protecting ICs
Research Manuscript GLite: A Fast and Efficient Automatic Graph-Level Optimizer for Large-Scale DNNs
Engineering Tracks Power Aware Scan Structure Planner
Research Manuscript FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
Research Manuscript HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression
Research Manuscript DA PUF: Dual-State Analog PUF
Research Manuscript Learn about advanced placement algorithms for hyperscaler chips!
Networking Reception Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Research Manuscript InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Research Manuscript HIMap: A Heuristic and Iterative Logic Synthesis Approach
Research Manuscript Tailor: Removing Redundancy in Memristive Analog Neural Network Accelerators
Research Manuscript Scalable Crash Consistency for Secure Persistent Memory
Research Manuscript MetaZip: A High-throughput and Efficient Accelerator for DEFLATE
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript MetaZip: A High-throughput and Efficient Accelerator for DEFLATE
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Networking Reception Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Research Manuscript PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript Floorplanning with Graph Attention
Research Manuscript On-Chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks
Research Manuscript RobustQNN: Noise-Aware Training for Robust Quantum Neural Networks
Research Manuscript Pushing the Boundaries of Practical AI: Efficiency and Robustness
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Networking Reception Enabling Versatile Power Management for AIoT Devices
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Research Manuscript EMS: Efficient Memory Subsystem Synthesis for Spatial Accelerators
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Networking Reception Addressing Ordering Woes of PCIe with Formal Verification
Networking Reception Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Track Poster Efficient Custom Logic P&R Flow using Virtual Hierarchy
Engineering Track Poster Back End of Line Process-aware Static Timing Analysis
Engineering Track Poster Static Timing and Power Analysis with Process Space Exploration
Engineering Tracks Machine Learning and EDA: The Productivity Cycle
Research Panel Heterogeneous 3D or Monolithic 3D, Which Direction to Go?
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Networking Reception A Built-In Adaptive NDA for High-Level Language Acceleration
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Networking Reception Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Research Manuscript Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Research Manuscript NovelRewrite: Node-Level Parallel AIG Rewriting
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Networking Reception ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS
Research Manuscript Differentiable Timing Driven Global Placement
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
Research Manuscript Pushing the Boundaries of Practical AI: Efficiency and Robustness
Engineering Tracks Maximize GPGPU performance-per-watt across real scenarios with 10x efficient power solution
Engineering Track Poster Power solution to maximize performance-per-watt for GPGPU
Networking Reception A Coq Framework for More Trustworthy DRAM Controllers
Research Manuscript Accurate Timing Prediction at Placement Stage with Look-Ahead RC Network
Networking Reception Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
Research Manuscript Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Research Manuscript Winograd Convolution: A Perspective from Fault Tolerance
Research Manuscript SSD: Storage Supremacy for lifelong Data
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Networking Reception Enabling Versatile Power Management for AIoT Devices
Engineering Track Poster Minimize Power Consumption with A Novel Power ECO Flow
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript NovelRewrite: Node-Level Parallel AIG Rewriting
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Research Manuscript Efficient Access Scheme for Multi-bank Based NTT Architecture Through Conflict Graph
Research Manuscript MC-CIM: A Reconfigurable Computation-In-Memory For Efficient Stereo Matching Cost Computation
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript Xplace: An Extremely Fast and Extensible Global Placement Framework
Research Manuscript Adaptive Window-Based Sensor Attack Detection for Cyber-Physical Systems
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Networking Reception Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Manuscript NovelRewrite: Node-Level Parallel AIG Rewriting
Networking Reception Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Do Not Forget the Software: Bare Metal Neural Acceleration is no fun without it.
Research Manuscript LeHDC: Learning-Based Hyperdimensional Computing Classifier
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Research Manuscript Floorplanning with Graph Attention
Research Manuscript SS-LRU: A Smart Segmented LRU Caching for Storage System
Networking Reception Improving GPU Performance via Coordinated Kernel Slicing and Multi CUDA Streaming
Networking Reception Attacking the TimingCamouflage+ Algorithm
Networking Reception Logic Locking Based Trojans: A Friend Turns Foe
Engineering Tracks Novel Approach to Early detection of Metastability related issues
Research Panel Heterogeneous 3D or Monolithic 3D, Which Direction to Go?
Engineering Track Poster A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Engineering Tracks Novel Approach to Early detection of Metastability related issues
Research Manuscript Using Machine Learning to Optimize Graph Execution on NUMA Machines
Networking Reception Automatic Generation of Cell Based structured CIM Macros
Networking Reception FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Networking Reception MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript Raven: A Novel Kernel Debugging Tool on RISC-V
Research Manuscript AL-PA: Cross-Device Profiled Side-Channel Attack using Adversarial Learning
Research Manuscript Exploiting Data Locality in Memory for ORAM to Reduce Memory Access Overheads
Research Manuscript Tailor: Removing Redundancy in Memristive Analog Neural Network Accelerators
Research Manuscript Optimizing Quantum Circuit Placement via Machine Learning
Engineering Track Poster Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
Research Manuscript Improving LUT-Based Optimization for ASIC
Research Manuscript Winograd Convolution: A Perspective from Fault Tolerance
Networking Reception An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Research Manuscript Precise and Scalable Shared Cache Contention Analysis for WCET Estimation
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
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Networking Reception Addressing Ordering Woes of PCIe with Formal Verification
Engineering Track Poster Library Analytics and Library Partitioning [LALP] for PPA Efficiency
Research Manuscript CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Networking Reception Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Research Manuscript Silicon Validation of LUT-based Logic-Locked IP Cores
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Research Manuscript Cool Interconnects for Cool Accelerators on Top of Congestion Free Place & Route
Research Manuscript A Defect Tolerance Framework for Improving Yield
Research Manuscript GNNIE: GNN Inference Engine with Load-balancing and Graph-specific Caching
Networking Reception TrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
Networking Reception System-Level Design and Target Agnostic High-Level Optimizations for HLS
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
Special Session (Research) Large-scale Model-free Feature Selection and Visualization
Research Manuscript BlueSeer: AI-Driven Environment Detection via BLE Scans*
Engineering Tracks Verifying Register Maps with JasperGold: How Formal compares to UVM
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
Engineering Track Poster Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Engineering Track Poster Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios
Engineering Tracks Verifying Register Maps with JasperGold: How Formal compares to UVM
Engineering Track Poster Generation And Selection Of Universally Routable Via Mesh Specifications
Networking Reception A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Engineering Tracks Speeding-up Design Closure with Accurate Statistical Timing Macro-models
Networking Reception HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Engineering Track Poster SDR (Simulation-Driven Routing): A Solution to Get Electromigration Compliant Routing
Research Manuscript Designing Critical Systems with Iterative Automated Safety Analysis
Networking Reception SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
Networking Reception FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator
Engineering Track Poster Building a Robust Power Grid for Multi Million SoC using RedHawk-SC Early PG Grid Analysis
Networking Reception Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Panel What is the Future for Open-Source EDA?
Research Manuscript SEALS: Sensitivity-driven Efficient Approximate Logic Synthesis
Networking Reception A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Engineering Tracks Speeding-up Design Closure with Accurate Statistical Timing Macro-models
Special Session (Research) Automating Hardware Security Property Generation
Networking Reception Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Networking Reception Instant Data Sanitization on Multi-Level-Cell NAND Flash Memory
Engineering Track Poster Machine Learning Techniques for PDK Development Efficiency
Special Session (Research) Quantum Algorithm Design: A new tool for the design automation of quantum computing circuits
Networking Reception System-Level Design and Target Agnostic High-Level Optimizations for HLS
Networking Reception LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Research Manuscript Improving LUT-Based Optimization for ASIC
Engineering Track Poster Process Monitoring Blocks - for Monitoring Analog Performance
Engineering Track Poster A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage
Networking Reception Logic Locking Based Trojans: A Friend Turns Foe
Networking Reception Addressing Ordering Woes of PCIe with Formal Verification
Engineering Tracks SigmaDVD (sDVD): High Coverage Solution for Power Integrity Signoff
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
Engineering Track Poster Ensuring Accurate Crosstalk Analysis using CCS-Noise Liberty Model
Networking Reception Attacking the TimingCamouflage+ Algorithm
Engineering Track Poster Automated DCAP and filler cell insertion with embedded Design for Inspection (DFI) Sensors
Networking Reception A Proposition for Computing System Design Automaticity and Correctness Potential
Networking Reception RFR: An STT-MRAM Cache Management Scheme for Retention Failure Reduction
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
Networking Reception Fingerprinting Workloads for Reconfigurable Shared Accelerators
Research Manuscript GNNIE: GNN Inference Engine with Load-balancing and Graph-specific Caching
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Networking Reception Accelerating Data Analytics near Memory: A k-NN Search Case Study
Networking Reception Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Networking Reception Vector In Memory Architecture for simple and high efficiency computing
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Special Session (Research) A Distributed Approach to Silicon Compilation
Engineering Track Poster Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Research Manuscript Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing*
Engineering Track Poster AI-based Neural network approach for performance estimation of complex System-on-Chip
Networking Reception Circumventing Machine Learning-Based Attacks to Logic Locking
Engineering Track Poster In-design IR drop convergence with Ansys RHSC and SNPS fusion compiler
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Engineering Track Poster Design Timing Effects of Layer-to-Layer Interconnect Skew
Special Session (Research) Secure by Construction: Addressing Security Vulnerabilities Introduced During High-level Synthesis
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Engineering Track Poster AI-based Neural network approach for performance estimation of complex System-on-Chip
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Engineering Tracks New Directions in Silicon Solutions
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript Efficient Ensembles of Graph Neural Networks
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Engineering Tracks Encryption Interoperability with IEEE 1735
Networking Reception A Custom Macro Suite for Optimization of Neuromorphic TNN Designs in CMOS
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Networking Reception SoC Platform for Heterogeneous Multiple IP Core Evaluation
Engineering Tracks Optimization of hot/cold separation algorithm computation for SSD
Networking Reception Display Pixel Layout Design with Deep Reinforcement Learning
Networking Reception Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Engineering Track Poster SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION
Networking Reception HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Research Manuscript A Defect Tolerance Framework for Improving Yield
Research Manuscript Repeal Murphy's Law: Avoid Errors
Research Manuscript How Fast can you go? It is a mad, mad, mad, mad placement world!
Special Session (Research) Unsupervised learning for gate sizing
Networking Reception A Coq Framework for More Trustworthy DRAM Controllers
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Research Manuscript NAX: Neural Architecture and Memristive Xbar based Accelerator Co-design
Networking Reception HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Networking Reception Adaptive Sparsity-Aware Cloud Offloading for Edge DNN Inference
Special Session (Research) ScaleHLS: A Scalable High-Level Synthesis Framework on MLIR
Networking Reception AutoPilot: Compute Design Automation for Autonomous Drones
Research Manuscript Hexagons are the Bestagons: Design Automation for Silicon Dangling Bond Logic
Research Manuscript SEALS: Sensitivity-driven Efficient Approximate Logic Synthesis
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Engineering Track Poster Learnings from RDC Sign-Off on Low Power SoC
Research Manuscript Orders of Magnitude Acceleration
Research Manuscript Pref-X: A Framework to Reveal Data Prefetching in Commercial In-Order Cores
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
Networking Reception Automation of Functional Safety and Security Methods for Design and Verification
Networking Reception HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
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DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Engineering Tracks New Directions in Silicon Solutions
Networking Reception A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
Research Manuscript Fast and Scalable Human Pose Estimation using mmWave Point Cloud
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Networking Reception Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Research Manuscript Side Channels go Mainstream !!
Special Session (Research) A Distributed Approach to Silicon Compilation
Research Panel What is the Future for Open-Source EDA?
Networking Reception SoC Platform for Heterogeneous Multiple IP Core Evaluation
Engineering Track Poster A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
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Networking Reception RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Engineering Track Poster Thermal Aware Memory Controller Design with Chip Package System Simulation
Networking Reception Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Networking Reception Leveraging Layout-based Effects for Locking Analog ICs
Engineering Tracks Low Power Classes as extension to UVM Package Library
Special Session (Research) Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
Engineering Track Poster Smart Strategy to analyze CDC Violation related to IPs Interaction at SoC
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript On-Chip QNN: Towards Efficient On-Chip Training of Quantum Neural Networks
Research Manuscript RobustQNN: Noise-Aware Training for Robust Quantum Neural Networks
Networking Reception Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Engineering Track Poster Smart Strategy to analyze CDC Violation related to IPs Interaction at SoC
Research Manuscript AI and ML on next generation computing platforms
Engineering Track Poster FSDB based Self-Gating technique for Power saving and FEV Verification approaches
Engineering Track Poster PostMask functional ECO Implementation flow using Programmable cells
Engineering Track Poster Minimum repeater addition ECOs for power efficient designs
Engineering Track Poster Cell EM aware Design Optimization
Research Manuscript FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
Research Manuscript HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression
Engineering Track Poster Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios
Engineering Track Poster SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION
Engineering Track Poster Learnings from RDC Sign-Off on Low Power SoC
Engineering Track Poster Workflow Automation for SoC Performance Verification
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Networking Reception Accelerating Data Analytics near Memory: A k-NN Search Case Study
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Track Poster New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
Engineering Track Poster On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript A Fast and Scalable Qubit-Mapping Method for NoisyIntermediate-Scale Quantum Computers
Networking Reception Graph Partitioning Approach for Fast Quantum Circuit Simulation
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Tracks Extracting Source of Unknown Values in Transistor-level Logic Simulation
Engineering Track Poster Fast Design Space Exploration using RTL Architect for DRAM Designs
Engineering Track Poster A unified IP QA methodology to improve validation coverage and throughput
Engineering Track Poster Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Networking Reception AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript DETERRENT: Detecting Trojans using Reinforcement Learning
Research Manuscript Side Channels go Mainstream !!
Engineering Track Poster Physically Unclonable Function Compliant with ISO/IEC 20897-1:2020
Engineering Track Poster Machine Learning Techniques for PDK Development Efficiency
Design on Cloud Training How to run EDA tools on the Azure Cloud
Engineering Track Poster Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Engineering Tracks Speeding-up Design Closure with Accurate Statistical Timing Macro-models
Research Manuscript Equivalence Checking Paradigms in Quantum Circuit Design: A Case Study
Special Session (Research) The Basis of Design Tools for Quantum Computing: Arrays, Decision Diagrams, Tensor Networks, and more
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Research Manuscript Optimizing Parallel PREM Compilation over Nested Loop Structures
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