Contributors
A
Engineering Tracks Low Power Classes as extension to UVM Package Library
Work-in-Progress Poster Two-level Hierarchical Cluster-Node Scheduling for Heterogeneous Datacenters
Work-in-Progress Poster AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
DAC Pavilion Gladiator Arena Poster Battle Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors
Engineering Tracks Time Interleaving of Analog to Digital Converters Calibration Techniques
Work-in-Progress Poster HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Work-in-Progress Poster A Reinforcement Learning based Global Router
Back-End Design Intelligent Floorplanning (IFP)
Engineering Tracks Formal Verification of Deep Neural Networks in Hardware
Engineering Tracks Learnings from RDC Sign-Off on Low Power SoC
Work-in-Progress Poster Accelerating Data Analytics near Memory: A k-NN Search Case Study
Special Session (Research) Challenges and Opportunities for In-memory Compute
Work-in-Progress Poster Energy Profiling of USB DNN Accelerators
Work-in-Progress Poster AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Work-in-Progress Poster Leveraging Layout-based Effects for Locking Analog ICs
Research Panel Automating Analog Layout - Has the time finally come?
Research Manuscript Improving LUT-Based Optimization for ASIC
Work-in-Progress Poster System-Level Design and Target Agnostic High-Level Optimizations for HLS
Work-in-Progress Poster On the (in)security of Memory Protection Units
Work-in-Progress Poster AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript Fast and Scalable Human Pose Estimation using mmWave Point Cloud
Research Manuscript Do Not Forget the Software: Bare Metal Neural Acceleration is no fun without it.
Research Manuscript Embedded Systems in the Age of AI - Smart(er) Tools and Frameworks
Engineering Track Poster Shift Left Performance Verification using Formal Methods for ML ASICs
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Research Manuscript Resist Faults and Make Memories Smarter
Research Manuscript NAX: Neural Architecture and Memristive Xbar based Accelerator Co-design
Research Manuscript Response-Time Analysis for Deadline-Based Scheduling of ROS2
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Work-in-Progress Poster RFR: An STT-MRAM Cache Management Scheme for Retention Failure Reduction
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Work-in-Progress Poster A Coq Framework for More Trustworthy DRAM Controllers
Research Manuscript Bringing Source-Level Debugging Frameworks to Hardware Generators
Research Manuscript Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization
Research Manuscript Apple vs. EMA: Electromagnetic Side Channel Attacks on Apple CoreCrypto
Work-in-Progress Poster Leveraging Layout-based Effects for Locking Analog ICs
B
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Work-in-Progress Poster Bounded BaT: Bounded Backup Time for Intermittent Power Devices
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Engineering Tracks Learnings from RDC Sign-Off on Low Power SoC
Engineering Tracks Clustering Characterization Condition for Multi-bit Cell
Engineering Tracks Static Timing and Power Analysis with Process Space Exploration
Engineering Tracks PostMask functional ECO Implementation flow using Programmable cells
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Research Manuscript GTuner: Tuning DNN Computations on GPU via Graph Attention Network
Research Manuscript Automated Accelerator Optimization Aided by Graph Neural Networks
Special Session (Research) Democratizing Customized Computing with Automated Accelerator Synthesis
Engineering Tracks ML for Verification: Does it Work or Doesn’t It?
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Engineering Tracks Efficient Low Power Isolation Handling for Pre-Silicon Emulation
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
Back-End Design Pathways to Realizations
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Research Manuscript PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
Work-in-Progress Poster Endurance-Aware Deep Neural Network Real-Time Scheduling on ReRAM Accelerators
Research Panel What is the Future for Open-Source EDA?
Engineering Tracks Efficient Low Power Isolation Handling for Pre-Silicon Emulation
Engineering Tracks Digital Twin Reimagined - One Model To Rule Them All ?
Engineering Tracks ML for Verification: Does it Work or Doesn’t It?
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Work-in-Progress Poster Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis
Research Manuscript Cool Interconnects for Cool Accelerators on Top of Congestion Free Place & Route
Engineering Track Poster Path-Finding Through Variability-Aware DTCO-Flow
Back-End Design I/O Constraints Optimization
Work-in-Progress Poster Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Work-in-Progress Poster Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
Work-in-Progress Poster A Reinforcement Learning based Global Router
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Work-in-Progress Poster On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Engineering Tracks ML for Verification: Does it Work or Doesn’t It?
Special Session (Research) ADA, the Center for Applications Driving Architectures: Accomplishments and Vision Forward
DAC Pavilion Gladiator Arena Poster Battle Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Engineering Tracks Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Work-in-Progress Poster AutoPilot: Compute Design Automation for Autonomous Drones
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Work-in-Progress Poster A Custom Macro Suite for Optimization of Neuromorphic TNN Designs in CMOS
Back-End Design Pushing Boundaries - Challenges for Next-Generation Chip Design
Research Manuscript VIPR-PCB: A Machine Learning based Golden-Free PCB Assurance Framework
Research Manuscript Optimizing Quantum Circuit Synthesis for Permutations using Recursive Methods
Work-in-Progress Poster A Linear Column-Major Capacitance Multiplier based Analog In-Memory Computing Architecture
Engineering Tracks CDC Signoff Flow with DFT Logic
Work-in-Progress Poster TrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
Work-in-Progress Poster System-Level Design and Target Agnostic High-Level Optimizations for HLS
Work-in-Progress Poster Circumventing Machine Learning-Based Attacks to Logic Locking
Engineering Tracks Verifying Register Maps with JasperGold: How Formal compares to UVM
Work-in-Progress Poster Modular software for real-time quantum control systems
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Engineering Tracks Generation And Selection Of Universally Routable Via Mesh Specifications
Engineering Tracks Solving Antenna Errors for Hierarchical Designs
Engineering Tracks TCP/IP Hardware Stack Design and Verification Challenges
Work-in-Progress Poster A Coq Framework for More Trustworthy DRAM Controllers
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Work-in-Progress Poster Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Research Manuscript A Joint Management Middleware to Improve Training Performance of Deep Recommendation Systems with SSDs
Work-in-Progress Poster AutoPilot: Compute Design Automation for Autonomous Drones
Special Session (Research) Co-designing algorithms and hardware for efficient TinyML
Work-in-Progress Poster Modular software for real-time quantum control systems
Engineering Tracks Static Timing and Power Analysis with Process Space Exploration
Work-in-Progress Poster Instant Data Sanitization on Multi-Level-Cell NAND Flash Memory
Work-in-Progress Poster FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Research Manuscript Equivalence Checking Paradigms in Quantum Circuit Design: A Case Study
Research Manuscript Handling Non-Unitaries in Quantum Circuit Equivalence Checking
Special Session (Research) The Basis of Design Tools for Quantum Computing: Arrays, Decision Diagrams, Tensor Networks, and more
Research Panel Automating Analog Layout - Has the time finally come?
Work-in-Progress Poster A Reinforcement Learning based Global Router
C
Back-End Design I/O Constraints Optimization
Work-in-Progress Poster WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Work-in-Progress Poster A method for hierarchical, transistor-level circuit simulation
Research Manuscript AL-PA: Cross-Device Profiled Side-Channel Attack using Adversarial Learning
Research Manuscript Domain Knowledge-Infused Deep Learning for Automated Analog/RF Circuit Parameter Optimization*
Research Manuscript Hot Application and Cool Automation for Quantum Computing
Work-in-Progress Poster Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Work-in-Progress Poster A Built-In Adaptive NDA for High-Level Language Acceleration
Work-in-Progress Poster Aggressive Performance Improvement on PIM Devices by Adopting Hugepages
Work-in-Progress Poster Performance Impact of Inter-PIM Communication
Work-in-Progress Poster Vector In Memory Architecture for simple and high efficiency computing
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Engineering Tracks Automatic Checkpoint Support in the Device Modeling Language (DML)
Work-in-Progress Poster System-Level Design and Target Agnostic High-Level Optimizations for HLS
Back-End Design Timing Analytics and Reporting: From Design Start to Finish
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Work-in-Progress Poster Attacking the TimingCamouflage+ Algorithm
Research Manuscript NAX: Neural Architecture and Memristive Xbar based Accelerator Co-design
Engineering Tracks Shift Left DFT Sign-off Methodology for Edge AI Processor
Research Manuscript VIPR-PCB: A Machine Learning based Golden-Free PCB Assurance Framework
Research Manuscript Fast and Fiducius: Achieving Efficient Autonomy with Confidence
Work-in-Progress Poster Automation of Functional Safety and Security Methods for Design and Verification
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
Research Manuscript Keep moving up and looking sideways with verification boosters!
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Work-in-Progress Poster RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript Rethinking Key-Value Store for Byte-Addressable Optane Persistent Memory
Research Manuscript SSD: Storage Supremacy for lifelong Data
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript HCG: Optimizing Embedded Code Generation of Simulink with SIMD Instruction Synthesis
Research Manuscript Precise and Scalable Shared Cache Contention Analysis for WCET Estimation
Work-in-Progress Poster MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits
Research Manuscript CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints
Networking Reception Subgraph Matching Based Reference Placement for PCB Designs
Work-in-Progress Poster MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Special Session (Research) Using Logic to Understand Learning
Work-in-Progress Poster Joint Resource Scheduling in Wireless Networked Control Systems with Energy Constraint
Work-in-Progress Poster Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Engineering Track Poster AI assisted smart analysis (AISA) for system level issue localization in post silicon validation
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Work-in-Progress Poster ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript Optimizing Quantum Circuit Synthesis for Permutations using Recursive Methods
Work-in-Progress Poster Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
Special Session (Research) ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations
Research Manuscript From Cores to Memory and Back
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Research Manuscript GaBAN: A Generic and Flexibly Programmable Vector Neuro-processor on FPGA
DAC Pavilion Gladiator Arena Poster Battle Design Timing Effects of Layer-to-Layer Interconnect Skew
Research Manuscript CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs
Research Manuscript High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints
Networking Reception Subgraph Matching Based Reference Placement for PCB Designs
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Engineering Tracks A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Research Manuscript libcrpm: Improving the Checkpoint Performance of NVM
Research Manuscript HIMap: A Heuristic and Iterative Logic Synthesis Approach
Research Manuscript TAAS: A Timing-Aware Analytical Strategy for AQFP-Capable Placement Automation
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Networking Reception Flexible Chip Placement via Reinforcement Learning
Work-in-Progress Poster Modular software for real-time quantum control systems
Research Manuscript A Fast Parameter Tuning Framework via Transfer Learning and Multi-objective Bayesian Optimization
Work-in-Progress Poster Aging-aware Critical Path Selection via Graph Attentional Networks
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript Be Water: Adaptive AI for Dynamic Systems
Work-in-Progress Poster Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
Work-in-Progress Poster MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript DA PUF: Dual-State Analog PUF
Research Manuscript Novel approaches for scaling routing and DFM challenges
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Work-in-Progress Poster Enabling Versatile Power Management for AIoT Devices
Work-in-Progress Poster RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Research Manuscript A scalable symbolic simulation tool for low power embedded systems
Work-in-Progress Poster RFR: An STT-MRAM Cache Management Scheme for Retention Failure Reduction
Work-in-Progress Poster MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Engineering Tracks Low Power Classes as extension to UVM Package Library
Work-in-Progress Poster Ambient Temperature Estimation using Neural Networks and Device Contextual Information
Work-in-Progress Poster A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
Networking Reception Efficient Timing Propagation with Simultaneous Structural and Pipeline Parallelisms
Engineering Tracks Efficient Custom Logic P&R Flow using Virtual Hierarchy
Networking Reception Thermal-Aware Drone Battery Management
Engineering Tracks Fast Design Space Exploration using RTL Architect for DRAM Designs
Research Manuscript Bipolar Vector Classifier for Fault-tolerant Deep Neural Networks
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript CarM: Hierarchical Episodic Memory for Continual Learning
Work-in-Progress Poster Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Tracks Efficient Custom Logic P&R Flow using Virtual Hierarchy
Research Manuscript NN-LUT: Neural Approximation of Non-Linear Operations for Efficient Transformer Inference
Research Manuscript New Normal for In-Memory Computing: Novel Circuits and Systems
Engineering Tracks Extracting Source of Unknown Values in Transistor-level Logic Simulation
Engineering Tracks Fast Design Space Exploration using RTL Architect for DRAM Designs
Engineering Tracks New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks Cell EM aware Design Optimization
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Work-in-Progress Poster AMBITION: Ambient Temperature Aware VM Allocation for Energy Efficient Edge Data Centers
Work-in-Progress Poster AMBITION: Ambient Temperature Aware VM Allocation for Energy Efficient Edge Data Centers
Work-in-Progress Poster Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
Networking Reception Flexible Chip Placement via Reinforcement Learning
Work-in-Progress Poster RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Special Session (Research) Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
Work-in-Progress Poster Equivalence Checking for Agile Hardware Design
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Manuscript Designing ML-Resilient Locking at Register-Transfer Level
Research Manuscript Automated Accelerator Optimization Aided by Graph Neural Networks
Special Session (Research) Democratizing Customized Computing with Automated Accelerator Synthesis
Work-in-Progress Poster Vector In Memory Architecture for simple and high efficiency computing
DAC Pavilion Gladiator Arena Poster Battle A unified IP QA methodology to improve validation coverage and throughput
Back-End Design The Hardware/Software Nexus in Chip Design
Work-in-Progress Poster HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Research Manuscript Improving Compute In-Memory ECC Reliability with Successive Correction
Engineering Tracks Encryption Interoperability with IEEE 1735
Work-in-Progress Poster On the (in)security of Memory Protection Units
Research Manuscript VIPR-PCB: A Machine Learning based Golden-Free PCB Assurance Framework
Work-in-Progress Poster par-gem5: Parallelizing gem5’s Atomic Mode
Work-in-Progress Poster System-Level Design and Target Agnostic High-Level Optimizations for HLS
D
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Research Manuscript Heuristic Adaptability to Input Dynamics for SpMM on GPUs*
Work-in-Progress Poster WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems
Engineering Tracks Maximize GPGPU performance-per-watt across real scenarios with 10x efficient power solution
Engineering Tracks Power solution to maximize performance-per-watt for GPGPU
Work-in-Progress Poster Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Research Manuscript NobLSM: An LSM-tree with Non-blocking Writes for SSDs
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Work-in-Progress Poster A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Back-End Design Machine Learning and EDA: The Productivity Cycle
Back-End Design The Hardware/Software Nexus in Chip Design
Back-End Design The Hardware/Software Nexus in Chip Design
Research Manuscript Machine Learning for Resource Management: From Edge to Cloud
Engineering Tracks Shift Left DFT Sign-off Methodology for Edge AI Processor
Special Session (Research) A Systems driven approach to Semiconductor Research and Innovation
Research Panel Cryogenic Computing, Super Cool or Not?
Work-in-Progress Poster RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Work-in-Progress Poster Neural Network Layer Assignment for Distributed Inference via Integer Programming
Work-in-Progress Poster AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript Improving Compute In-Memory ECC Reliability with Successive Correction
Engineering Tracks Solving Antenna Errors for Hierarchical Designs
DAC Pavilion Panel How Robust is Your Hardware Security Program?
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Work-in-Progress Poster PRIME: A PRocessing In Memory HardwareEmulation Framework
Research Manuscript Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing*
Work-in-Progress Poster A Secure Design Methodology to Prevent Targeted Trojan Insertion During Fabrication
DAC Pavilion Gladiator Arena Poster Battle Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors
Engineering Tracks Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Work-in-Progress Poster RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
DAC Pavilion Gladiator Arena Poster Battle Design Timing Effects of Layer-to-Layer Interconnect Skew
Engineering Tracks Static Timing and Power Analysis with Process Space Exploration
Research Manuscript DA PUF: Dual-State Analog PUF
Engineering Tracks A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Research Manuscript Heuristic Adaptability to Input Dynamics for SpMM on GPUs*
Research Manuscript Robust Quantum Computing: Wild Goose Chase?
Work-in-Progress Poster AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Research Manuscript Floorplanning with Graph Attention
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Research Manuscript HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression
Work-in-Progress Poster RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Research Manuscript Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Work-in-Progress Poster Qualification of Metamorphic Relations for System Level AMS Models using Data Flow Coverage
Research Manuscript Robust Quantum Computing: Wild Goose Chase?
Research Manuscript Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Research Manuscript So You Want a Better Design? Go with Faster Timing and Lower Power Please!
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Work-in-Progress Poster Circumventing Machine Learning-Based Attacks to Logic Locking
Engineering Track Poster Mitigation of Soft-Errors in Storage Elements through Layout and Circuit Design Techniques
E
Work-in-Progress Poster HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Engineering Tracks Canceled: Design Considerations for Embedded at the Edge
Engineering Tracks Embedded Systems and Software
Work-in-Progress Poster Bridger: Fast Token Delivery in Elastic Circuits
Engineering Track Poster Clock Scripting for Reliable Design Flow
Engineering Track Poster AI assisted smart analysis (AISA) for system level issue localization in post silicon validation
Engineering Tracks TCP/IP Hardware Stack Design and Verification Challenges
Work-in-Progress Poster Aggressive Performance Improvement on PIM Devices by Adopting Hugepages
Work-in-Progress Poster Performance Impact of Inter-PIM Communication
Engineering Tracks Automatic Checkpoint Support in the Device Modeling Language (DML)
Back-End Design The Hardware/Software Nexus in Chip Design
Work-in-Progress Poster Tackling Resource Utilization in DNN Accelerators
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Engineering Track Poster Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
Engineering Track Poster Porting software to hardware using XLS/DSLX
Work-in-Progress Poster FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter
Research Manuscript PATH: Evaluation of Boolean Logic using Path-based In-Memory Computing
Research Manuscript Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization
Work-in-Progress Poster Aggressive Performance Improvement on PIM Devices by Adopting Hugepages
Work-in-Progress Poster Performance Impact of Inter-PIM Communication
F
Engineering Tracks Dealing with Silicon Aging in Digital Implementation using Library Metrics
Work-in-Progress Poster ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Work-in-Progress Poster Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Work-in-Progress Poster A Built-In Adaptive NDA for High-Level Language Acceleration
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
Special Session (Research) Secure by Construction: Addressing Security Vulnerabilities Introduced During High-level Synthesis
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
DAC Pavilion Gladiator Arena Poster Battle Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors
Work-in-Progress Poster AutoPilot: Compute Design Automation for Autonomous Drones
Work-in-Progress Poster Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Engineering Tracks Machine Learning Techniques for PDK Development Efficiency
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Back-End Design Characterization Challenges in System Level IO Interface
Work-in-Progress Poster Leveraging Layout-based Effects for Locking Analog ICs
Back-End Design Don't TikTok
Engineering Tracks Automated DCAP and filler cell insertion with embedded Design for Inspection (DFI) Sensors
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
DAC Pavilion Gladiator Arena Poster Battle A unified IP QA methodology to improve validation coverage and throughput
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript Xplace: An Extremely Fast and Extensible Global Placement Framework
Work-in-Progress Poster Joint Resource Scheduling in Wireless Networked Control Systems with Energy Constraint
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Research Manuscript Accurate Timing Prediction at Placement Stage with Look-Ahead RC Network
Special Session (Research) Automating Hardware Security Property Generation
DAC Pavilion Panel How Robust is Your Hardware Security Program?
G
Work-in-Progress Poster Deep Learning Empowered Spectrum Sensing and Access in Distributed Cognitive Radio Network
Work-in-Progress Poster Deep Reinforcement Learning Empowered Content Caching in Mobile Social Networks
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Manuscript Improving LUT-Based Optimization for ASIC
Work-in-Progress Poster A Reinforcement Learning based Global Router
Research Manuscript MetaZip: A High-throughput and Efficient Accelerator for DEFLATE
Special Session (Research) Shared Foundations for ML and EDA in the TILOS AI Institute
Work-in-Progress Poster Rubik’s Optical Neural Networks: Multi-task Learning with Physics-aware System and Algorithms
Work-in-Progress Poster Aging-aware Critical Path Selection via Graph Attentional Networks
Back-End Design Characterization Challenges in System Level IO Interface
Special Session (Research) High-level design methods for hardware security: Is it the right choice?
Work-in-Progress Poster Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
Back-End Design Timing Analytics and Reporting: From Design Start to Finish
Engineering Tracks Library Analytics and Library Partitioning [LALP] for PPA Efficiency
Engineering Track Poster Diagnosis of Faults by Fault Simulation on PCIe
Work-in-Progress Poster Automatic Generation of Cell Based structured CIM Macros
Work-in-Progress Poster Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
Engineering Tracks Library Analytics and Library Partitioning [LALP] for PPA Efficiency
Engineering Track Poster Diagnosis of Faults by Fault Simulation on PCIe
Work-in-Progress Poster A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
DAC Pavilion Panel Those Darn Bugs! When Will They be Exterminated for Good?
Engineering Track Poster Formal based Automation Framework to Verify Coherent Connectivity of Multi-instance IPs
Engineering Track Poster Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement
Work-in-Progress Poster Bounded BaT: Bounded Backup Time for Intermittent Power Devices
Research Manuscript DETERRENT: Detecting Trojans using Reinforcement Learning
Research Manuscript Timing-Critical Design
Work-in-Progress Poster On the (in)security of Memory Protection Units
Research Manuscript Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Research Manuscript Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Networking Reception Waveform-based Performance Analysis of RISC-V Processors
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Special Session (Research) The Basis of Design Tools for Quantum Computing: Arrays, Decision Diagrams, Tensor Networks, and more
Research Manuscript AL-PA: Cross-Device Profiled Side-Channel Attack using Adversarial Learning
Research Manuscript GEML: GNN-Based Efficient Mapping Method for Large Loop Applications on CGRA
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript QOC: Quantum On-Chip Training with Parameter Shift and Gradient Pruning
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript Optimizing Parallel PREM Compilation over Nested Loop Structures
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
Work-in-Progress Poster Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Work-in-Progress Poster Two-level Hierarchical Cluster-Node Scheduling for Heterogeneous Datacenters
Work-in-Progress Poster RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
Work-in-Progress Poster Bridger: Fast Token Delivery in Elastic Circuits
Engineering Track Poster Physically Unclonable Function Compliant with ISO/IEC 20897-1:2020
Research Manuscript CamSkyGate: Camouflaged Skyrmion Gates for Protecting ICs
Research Manuscript Iterate and Scale: Designing Stronger and Safer Embedded Systems
Work-in-Progress Poster Automation of Functional Safety and Security Methods for Design and Verification
Engineering Tracks Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Research Manuscript Optimizing Quantum Circuit Placement via Machine Learning
Research Manuscript DETERRENT: Detecting Trojans using Reinforcement Learning
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
Research Manuscript Designing Critical Systems with Iterative Automated Safety Analysis
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Research Manuscript Accurate Timing Prediction at Placement Stage with Look-Ahead RC Network
Work-in-Progress Poster Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Manuscript Response-Time Analysis for Deadline-Based Scheduling of ROS2
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS
Research Manuscript Differentiable Timing Driven Global Placement
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Back-End Design I/O Constraints Optimization
Work-in-Progress Poster On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster
Engineering Tracks Efficient Low Power Isolation Handling for Pre-Silicon Emulation
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Work-in-Progress Poster Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Research Manuscript Apple vs. EMA: Electromagnetic Side Channel Attacks on Apple CoreCrypto
Work-in-Progress Poster AI-Driven Accelerometer-Based Bird Activity Recognition
Research Manuscript Thinking Fast and Acting Smart: Accelerated and Intelligent IoT
Engineering Track Poster History based Physical Synthesis
Research Manuscript GEML: GNN-Based Efficient Mapping Method for Large Loop Applications on CGRA
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Engineering Tracks Static Timing and Power Analysis with Process Space Exploration
Research Manuscript Solving Traveling Salesman Problems via a Parallel Fully Connected Ising Machine
Work-in-Progress Poster Joint Resource Scheduling in Wireless Networked Control Systems with Energy Constraint
Work-in-Progress Poster Joint Resource Scheduling in Wireless Networked Control Systems with Energy Constraint
Engineering Tracks Efficient read/write turn-around policy of LPDDR5 memory controller
Engineering Tracks Digital Twin Reimagined - One Model To Rule Them All ?
Tutorial A Journey to SW/HW Co-design in Machine Learning: Fundamental, Advancement, and Application
Work-in-Progress Poster Error Distribution Modeling for Behavior-level Approximate Computing
Research Manuscript H2H: Heterogeneous Model to Heterogeneous System Mapping with Computation and Communication Awareness
Research Manuscript High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
Work-in-Progress Poster Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information
Research Manuscript So You Want a Better Design? Go with Faster Timing and Lower Power Please!
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Work-in-Progress Poster AI-Driven Accelerometer-Based Bird Activity Recognition
Research Manuscript BlueSeer: AI-Driven Environment Detection via BLE Scans*
Work-in-Progress Poster SoC Platform for Heterogeneous Multiple IP Core Evaluation
Work-in-Progress Poster Qualification of Metamorphic Relations for System Level AMS Models using Data Flow Coverage
Engineering Tracks DVD Diagnostics - Debugging Dynamic IR problems using Advanced Analytics
Networking Reception Subgraph Matching Based Reference Placement for PCB Designs
Research Manuscript Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception
Research Manuscript Novel Circuits for PIM
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
Research Manuscript A scalable symbolic simulation tool for low power embedded systems
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
DAC Pavilion Gladiator Arena Poster Battle Billion Instance Timing Sign-off
Work-in-Progress Poster Fingerprinting Workloads for Reconfigurable Shared Accelerators
Work-in-Progress Poster MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Work-in-Progress Poster Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Engineering Tracks Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Tracks Static Timing and Power Analysis with Process Space Exploration
Engineering Tracks Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Research Manuscript Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
DAC Pavilion Panel Women in Engineering: Real Advice for Today’s Female Engineers
Special Session (Research) The Basis of Design Tools for Quantum Computing: Arrays, Decision Diagrams, Tensor Networks, and more
Engineering Tracks Design Considerations for Embedded at the Edge
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Work-in-Progress Poster A Secure Design Methodology to Prevent Targeted Trojan Insertion During Fabrication
DAC Pavilion Panel Women in Engineering: Real Advice for Today’s Female Engineers
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Engineering Tracks Workflow Automation for SoC Performance Verification
Work-in-Progress Poster Constructing Large Buffers with HeterogeneousSTT-RAM Cells for DNN Accelerators
Research Manuscript Bringing Source-Level Debugging Frameworks to Hardware Generators
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Work-in-Progress Poster Adaptive Sparsity-Aware Cloud Offloading for Edge DNN Inference
Work-in-Progress Poster Enabling Versatile Power Management for AIoT Devices
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Work-in-Progress Poster ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Work-in-Progress Poster ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Networking Reception Flexible Chip Placement via Reinforcement Learning
Engineering Tracks Automated Timing-aware Dynamic Voltage Drop ECO
DAC Pavilion Gladiator Arena Poster Battle Design Timing Effects of Layer-to-Layer Interconnect Skew
Research Manuscript Cost-Efficient Analog and Stochastic Computing Techniques for Deep Learning
Work-in-Progress Poster ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript From machine learning to graphs: a new wave towards analog design
Research Manuscript H2H: Heterogeneous Model to Heterogeneous System Mapping with Computation and Communication Awareness
Research Manuscript Is Persistent Memory Real?
Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Research Manuscript ODHD: One-Class Hyperdimensional Computing for Outlier Detection
Research Manuscript SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators
Research Manuscript NobLSM: An LSM-tree with Non-blocking Writes for SSDs
Work-in-Progress Poster Circumventing Machine Learning-Based Attacks to Logic Locking
Work-in-Progress Poster Deep Reinforcement Learning Empowered Content Caching in Mobile Social Networks
Research Manuscript GuardNN: Secure Accelerator Architecture for Privacy-Preserving Deep Learning
Research Manuscript Scalable Crash Consistency for Secure Persistent Memory
Research Manuscript Heuristic Adaptability to Input Dynamics for SpMM on GPUs*
Research Manuscript Winograd Convolution: A Perspective from Fault Tolerance
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Work-in-Progress Poster An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Networking Reception Efficient Timing Propagation with Simultaneous Structural and Pipeline Parallelisms
Research Manuscript DeepGate: Learning Neural Representations of Logic Gates*
Research Manuscript Functionality Matters in Netlist Representation Learning
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Engineering Tracks Solving Antenna Errors for Hierarchical Designs
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript Pref-X: A Framework to Reveal Data Prefetching in Commercial In-Order Cores
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
DAC Pavilion Gladiator Arena Poster Battle Design Timing Effects of Layer-to-Layer Interconnect Skew
DAC Pavilion Gladiator Arena Poster Battle Minimize Power Consumption with A Novel Power ECO Flow
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Special Session (Research) Secure by Construction: Addressing Security Vulnerabilities Introduced During High-level Synthesis
Work-in-Progress Poster Bridger: Fast Token Delivery in Elastic Circuits
Work-in-Progress Poster SoC Platform for Heterogeneous Multiple IP Core Evaluation
Work-in-Progress Poster Graph Partitioning Approach for Fast Quantum Circuit Simulation
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Research Manuscript Energy Efficient Data Search Design and Optimization Based on A Compact Ferroelectric FET Content Addressable Memory
Research Manuscript HDPG: Hyperdimensional Policy-based Reinforcement Learning for Continuous Control
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Engineering Track Poster Is Front-End Analog Design Automation an NP-type or simply a P-type problem ?
Work-in-Progress Poster EA-Prune: Environment Adaptive Neural Network Pruning for Low-power Energy Harvesting Devices
Work-in-Progress Poster Energy Profiling of USB DNN Accelerators
Research Panel Heterogeneous 3D or Monolithic 3D, Which Direction to Go?
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
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Work-in-Progress Poster A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Work-in-Progress Poster Addressing Ordering Woes of PCIe with Formal Verification
Work-in-Progress Poster Ambient Temperature Estimation using Neural Networks and Device Contextual Information
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Work-in-Progress Poster CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs
Special Session (Research) Prospects and Challenges for TinyML
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Work-in-Progress Poster AutoPilot: Compute Design Automation for Autonomous Drones
Work-in-Progress Poster A Model-Based Evaluation Framework for Battery Cell Balancing Techniques
Engineering Tracks Optimization of hot/cold separation algorithm computation for SSD
Work-in-Progress Poster Energy Profiling of USB DNN Accelerators
Work-in-Progress Poster RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Research Manuscript Optimizing Quantum Circuit Synthesis for Permutations using Recursive Methods
Special Session (Research) Quantum Information Science with Qiskit
Work-in-Progress Poster Logic Locking Based Trojans: A Friend Turns Foe
Design on Cloud Training Google Cloud Training
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript CarM: Hierarchical Episodic Memory for Continual Learning
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Special Session (Research) ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks Automated Timing-aware Dynamic Voltage Drop ECO
Back-End Design Thermal-aware Power and Performance Simulator
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Work-in-Progress Poster FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter
Research Manuscript PATH: Evaluation of Boolean Logic using Path-based In-Memory Computing
Research Manuscript Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
Engineering Track Poster Performance Optimization of Embedded FPGA
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Research Manuscript EMS: Efficient Memory Subsystem Synthesis for Spatial Accelerators
Research Manuscript A2-ILT: GPU Accelerated ILT with Spatial Attention Mechanism
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Work-in-Progress Poster Improving GPU Performance via Coordinated Kernel Slicing and Multi CUDA Streaming
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Research Manuscript Efficient Bayesian Yield Analysis and Optimization with Active Learning
Work-in-Progress Poster EA-Prune: Environment Adaptive Neural Network Pruning for Low-power Energy Harvesting Devices
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Engineering Tracks Learnings from RDC Sign-Off on Low Power SoC
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Work-in-Progress Poster par-gem5: Parallelizing gem5’s Atomic Mode
Back-End Design New Directions in Silicon Solutions
Research Manuscript Future Unleashed: Beyond-CMOS Meets the Real World
Work-in-Progress Poster Bridger: Fast Token Delivery in Elastic Circuits
Engineering Tracks Thermal Aware Memory Controller Design with Chip Package System Simulation
Research Manuscript Precise and Scalable Shared Cache Contention Analysis for WCET Estimation
Research Manuscript Floorplanning with Graph Attention
Special Session (Research) ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations
Engineering Tracks Workflow Automation for SoC Performance Verification
Engineering Tracks ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Engineering Tracks Cell EM aware Design Optimization
Special Session (Research) MRAM In - memory Computing Crossbar Array
Work-in-Progress Poster SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
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Work-in-Progress Poster A Linear Column-Major Capacitance Multiplier based Analog In-Memory Computing Architecture
Research Manuscript Silicon Validation of LUT-based Logic-Locked IP Cores
Work-in-Progress Poster System-Level Design and Target Agnostic High-Level Optimizations for HLS
Research Panel What is the Future for Open-Source EDA?
DAC Pavilion Panel Bespoke Silicon - Tailor-Made for Maximum Performance
Research Manuscript DETERRENT: Detecting Trojans using Reinforcement Learning
Engineering Tracks UPF Restructuring Flow Based On Power Promotion and Demotion Capabilities
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript A Near-Storage Framework for Boosted Data Preprocessing of Mass Spectrum Clustering
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Engineering Tracks Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Research Manuscript New Normal for In-Memory Computing: Novel Circuits and Systems
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks Cell EM aware Design Optimization
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Research Manuscript A Fast and Scalable Qubit-Mapping Method for NoisyIntermediate-Scale Quantum Computers
Work-in-Progress Poster Graph Partitioning Approach for Fast Quantum Circuit Simulation
Back-End Design Power Aware Scan Structure Planner
Work-in-Progress Poster Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations
Work-in-Progress Poster FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Engineering Track Poster Path-Finding Through Variability-Aware DTCO-Flow
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Manuscript Designing ML-Resilient Locking at Register-Transfer Level
Special Session (Research) High-level design methods for hardware security: Is it the right choice?
Work-in-Progress Poster Too Big to Fail? Active Few-shot Learning Guided Logic Synthesis
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Special Session (Research) Automating Hardware Security Property Generation
Engineering Track Poster Diagnosis of Faults by Fault Simulation on PCIe
Engineering Tracks Low Power Classes as extension to UVM Package Library
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Research Panel Cryogenic Computing, Super Cool or Not?
Work-in-Progress Poster TrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
Research Manuscript Zhuyi: Perception Processing Rate Estimation for Safety of Autonomous Vehicles
Work-in-Progress Poster AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Research Manuscript Designing Critical Systems with Iterative Automated Safety Analysis
Engineering Tracks Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
Research Panel Automating Analog Layout - Has the time finally come?
Research Manuscript GATSPI: GPU Accelerated Gate-Level Simulation for Power Improvement
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
Research Manuscript DeepGate: Learning Neural Representations of Logic Gates*
Work-in-Progress Poster Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Back-End Design I/O Constraints Optimization
Engineering Tracks Fast Design Space Exploration using RTL Architect for DRAM Designs
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Engineering Tracks Optimization of hot/cold separation algorithm computation for SSD
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Engineering Tracks Efficient Custom Logic P&R Flow using Virtual Hierarchy
Engineering Tracks Workflow Automation for SoC Performance Verification
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks Fast Design Space Exploration using RTL Architect for DRAM Designs
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Engineering Tracks Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Research Manuscript Voltage Prediction of Drone Battery Reflecting Internal Temperature
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Work-in-Progress Poster A Page-mapping Consistency Protecting Method for Soft Error Damage in Flash-based Storage
Work-in-Progress Poster Modular software for real-time quantum control systems
Work-in-Progress Poster Modular software for real-time quantum control systems
Engineering Tracks Automated Timing-aware Dynamic Voltage Drop ECO
Engineering Tracks Extracting Source of Unknown Values in Transistor-level Logic Simulation
Engineering Tracks ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Engineering Tracks Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
Back-End Design Design Rule Decision Methodology For Balancing Process Limit and Routability Improvement
DAC Pavilion Gladiator Arena Poster Battle Minimize Power Consumption with A Novel Power ECO Flow
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
DAC Pavilion Gladiator Arena Poster Battle Minimize Power Consumption with A Novel Power ECO Flow
Engineering Tracks Learning-based Power Modeling for Versal AI Engine
Work-in-Progress Poster AMBITION: Ambient Temperature Aware VM Allocation for Energy Efficient Edge Data Centers
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks Efficient read/write turn-around policy of LPDDR5 memory controller
Engineering Track Poster The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud
Engineering Tracks Efficient read/write turn-around policy of LPDDR5 memory controller
Back-End Design Implementing QDI Design with Conventional Synchronous Design Flow: A Case of Long Distance Interconnect across Voltage Domain
Engineering Tracks ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Engineering Tracks Workflow Automation for SoC Performance Verification
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Engineering Tracks Fast Design Space Exploration using RTL Architect for DRAM Designs
Engineering Tracks Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Work-in-Progress Poster Constructing Large Buffers with HeterogeneousSTT-RAM Cells for DNN Accelerators
Work-in-Progress Poster AMBITION: Ambient Temperature Aware VM Allocation for Energy Efficient Edge Data Centers
Work-in-Progress Poster A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
DAC Pavilion Panel Bespoke Silicon - Tailor-Made for Maximum Performance
Networking Reception Waveform-based Performance Analysis of RISC-V Processors
Work-in-Progress Poster WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems
Research Manuscript Highly-Optimized Yet Flexible Neuromorphic Processors
Work-in-Progress Poster Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Tracks Thermal Aware Memory Controller Design with Chip Package System Simulation
Work-in-Progress Poster Novel ML based Reconfigurable Macro Placement for SoC Design
Work-in-Progress Poster DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms
Engineering Tracks PostMask functional ECO Implementation flow using Programmable cells
Research Manuscript Adaptive Window-Based Sensor Attack Detection for Cyber-Physical Systems
Research Manuscript Can We Achieve a Secure, Robust, and Energy-efficient Cloud-Edge Continuum?
Work-in-Progress Poster AMBITION: Ambient Temperature Aware VM Allocation for Energy Efficient Edge Data Centers
Engineering Tracks Generation And Selection Of Universally Routable Via Mesh Specifications
Engineering Tracks Solving Antenna Errors for Hierarchical Designs
Engineering Tracks ROHD: The Rapid Open Hardware Development Framework
Research Manuscript GEML: GNN-Based Efficient Mapping Method for Large Loop Applications on CGRA
Research Manuscript Preventing Brain Drain: How to Secure Next Generation AI
Work-in-Progress Poster Energy Profiling of USB DNN Accelerators
Engineering Tracks Thermal Aware Memory Controller Design with Chip Package System Simulation
Work-in-Progress Poster A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
Work-in-Progress Poster AutoPilot: Compute Design Automation for Autonomous Drones
Research Manuscript Efficiency Attacks on Spiking Neural Networks
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Research Manuscript Exploiting Data Locality in Memory for ORAM to Reduce Memory Access Overheads
DAC Pavilion Panel How Robust is Your Hardware Security Program?
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Research Panel Approximate Computing, Fiction or Reality?
Research Manuscript DELTA: DEsigning a steaLthy trigger mechanism for analog hardware Trojans and its detection Analysis
Research Manuscript SSD: Storage Supremacy for lifelong Data
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Research Manuscript Adaptive Neural Recovery for Highly Robust Brain-like Representation
Engineering Tracks Ensuring Accurate Crosstalk Analysis using CCS-Noise Liberty Model
Engineering Track Poster Design Intent Driven Analog Routing Methodology
Research Manuscript GNNIE: GNN Inference Engine with Load-balancing and Graph-specific Caching
Research Manuscript Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing*
Research Manuscript Pipette: Efficient Fine-Grained Reads for SSDs
Work-in-Progress Poster Modular software for real-time quantum control systems
Work-in-Progress Poster Fast In-Memory Floating-Point Addition
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
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Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Work-in-Progress Poster MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Special Session (Research) Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
Engineering Track Poster Improving Power Grid IR drop with an automated layout enhancement flow
Work-in-Progress Poster Automatic Generation of Cell Based structured CIM Macros
Work-in-Progress Poster AI-Driven Accelerometer-Based Bird Activity Recognition
Research Manuscript BlueSeer: AI-Driven Environment Detection via BLE Scans*
Work-in-Progress Poster Design Space Exploration of Mixed-Precision Hardware Accelerators for CNNs
Research Manuscript Improving LUT-Based Optimization for ASIC
DAC Pavilion Gladiator Arena Poster Battle Billion Instance Timing Sign-off
Work-in-Progress Poster AI/ML Driven Self-adaptive Design Methodology for Analog Circuits
Engineering Tracks Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Engineering Tracks Automated Timing-aware Dynamic Voltage Drop ECO
Work-in-Progress Poster Lego: Dynamic Multi-Chip-Module Resource Provision Architecture for Multi-Tenant DNNs
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Engineering Track Poster FPopt: ML-Based Chip Floorplan Optimization
Engineering Tracks Efficient Custom Logic P&R Flow using Virtual Hierarchy
Research Manuscript Neural Computation for Robust and Holographic Face Detection
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Tracks Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
DAC Pavilion Panel Bespoke Silicon - Tailor-Made for Maximum Performance
Engineering Tracks Efficient Custom Logic P&R Flow using Virtual Hierarchy
Engineering Tracks Clustering Characterization Condition for Multi-bit Cell
Engineering Tracks Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
Research Manuscript Timing Macro Modeling with Graph Neural Networks
Engineering Tracks ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Engineering Tracks New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits
Research Manuscript CarM: Hierarchical Episodic Memory for Continual Learning
Engineering Tracks Clustering Characterization Condition for Multi-bit Cell
Networking Reception Flexible Chip Placement via Reinforcement Learning
Research Manuscript Bipolar Vector Classifier for Fault-tolerant Deep Neural Networks
Engineering Tracks ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
Work-in-Progress Poster Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information
Work-in-Progress Poster A Page-mapping Consistency Protecting Method for Soft Error Damage in Flash-based Storage
Engineering Tracks Dynamic CDC Verification with Enhanced Jitter Modeling in Synchronizers
Networking Reception Thermal-Aware Drone Battery Management
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Work-in-Progress Poster Addressing Ordering Woes of PCIe with Formal Verification
Work-in-Progress Poster Fast In-Memory Floating-Point Addition
Research Manuscript Designing ML-Resilient Locking at Register-Transfer Level
Engineering Tracks Rapid Embedded Software Verification Through Hardware-Accelerated, Parallel SystemC TLM Simulation - A RISC-V Example
Work-in-Progress Poster X-on-X Simulation: Distributed Parallel SystemC TLM Virtual Platforms for Heterogeneous Systems
Work-in-Progress Poster par-gem5: Parallelizing gem5’s Atomic Mode
Engineering Track Poster History based Physical Synthesis
Work-in-Progress Poster Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
Networking Reception Placement Initialization via a Projected Eigenvector Algorithm
Work-in-Progress Poster Enabling Versatile Power Management for AIoT Devices
Research Manuscript SS-LRU: A Smart Segmented LRU Caching for Storage System
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript TAAS: A Timing-Aware Analytical Strategy for AQFP-Capable Placement Automation
Research Manuscript InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Work-in-Progress Poster ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Research Manuscript GLite: A Fast and Efficient Automatic Graph-Level Optimizer for Large-Scale DNNs
Work-in-Progress Poster Improving GPU Performance via Coordinated Kernel Slicing and Multi CUDA Streaming
Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Research Manuscript DeepGate: Learning Neural Representations of Logic Gates*
Work-in-Progress Poster Joint Resource Scheduling in Wireless Networked Control Systems with Energy Constraint
Research Manuscript CamSkyGate: Camouflaged Skyrmion Gates for Protecting ICs
Research Manuscript GLite: A Fast and Efficient Automatic Graph-Level Optimizer for Large-Scale DNNs
Back-End Design Power Aware Scan Structure Planner
Research Manuscript FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
Research Manuscript HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression
Research Manuscript DA PUF: Dual-State Analog PUF
Research Manuscript Learn about advanced placement algorithms for hyperscaler chips!
Work-in-Progress Poster Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Research Manuscript InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Research Manuscript HIMap: A Heuristic and Iterative Logic Synthesis Approach
Research Manuscript Tailor: Removing Redundancy in Memristive Analog Neural Network Accelerators
Research Manuscript Scalable Crash Consistency for Secure Persistent Memory
Research Manuscript MetaZip: A High-throughput and Efficient Accelerator for DEFLATE
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript MetaZip: A High-throughput and Efficient Accelerator for DEFLATE
Research Manuscript L-QoCo: Learning to Optimize Cache Capacity Overload Problem in Storage Systems
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Work-in-Progress Poster Rubik’s Optical Neural Networks: Multi-task Learning with Physics-aware System and Algorithms
Work-in-Progress Poster Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Research Manuscript PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript Floorplanning with Graph Attention
Research Manuscript Be Water: Adaptive AI for Dynamic Systems
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Work-in-Progress Poster Enabling Versatile Power Management for AIoT Devices
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Work-in-Progress Poster EA-Prune: Environment Adaptive Neural Network Pruning for Low-power Energy Harvesting Devices
Research Manuscript EMS: Efficient Memory Subsystem Synthesis for Spatial Accelerators
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Work-in-Progress Poster Addressing Ordering Woes of PCIe with Formal Verification
Work-in-Progress Poster Accelerating Data Analytics near Memory: A k-NN Search Case Study
Engineering Tracks Efficient Custom Logic P&R Flow using Virtual Hierarchy
Engineering Tracks Back End of Line Process-aware Static Timing Analysis
Engineering Tracks Static Timing and Power Analysis with Process Space Exploration
Back-End Design Machine Learning and EDA: The Productivity Cycle
Research Panel Heterogeneous 3D or Monolithic 3D, Which Direction to Go?
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Work-in-Progress Poster A Built-In Adaptive NDA for High-Level Language Acceleration
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Work-in-Progress Poster Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Research Manuscript Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Research Manuscript NovelRewrite: Node-Level Parallel AIG Rewriting
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Work-in-Progress Poster ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS
Research Manuscript Differentiable Timing Driven Global Placement
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
Research Manuscript Pushing the Boundaries of Practical AI: Efficiency and Robustness
Engineering Tracks Maximize GPGPU performance-per-watt across real scenarios with 10x efficient power solution
Engineering Tracks Power solution to maximize performance-per-watt for GPGPU
Work-in-Progress Poster A Coq Framework for More Trustworthy DRAM Controllers
Research Manuscript Accurate Timing Prediction at Placement Stage with Look-Ahead RC Network
Work-in-Progress Poster Powering Multi-Task Federated Learning with Competitive GPU Resource Sharing
Research Manuscript Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception
Research Manuscript VStore: In-Storage Graph Based Vector Search Accelerator
Research Manuscript Winograd Convolution: A Perspective from Fault Tolerance
Work-in-Progress Poster An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Work-in-Progress Poster Enabling Versatile Power Management for AIoT Devices
DAC Pavilion Gladiator Arena Poster Battle Minimize Power Consumption with A Novel Power ECO Flow
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript NovelRewrite: Node-Level Parallel AIG Rewriting
Research Manuscript Partition and Place Finite Element Model on Wafer Scale Engine
Work-in-Progress Poster An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Research Manuscript Efficient Access Scheme for Multi-bank Based NTT Architecture Through Conflict Graph
Research Manuscript MC-CIM: A Reconfigurable Computation-In-Memory For Efficient Stereo Matching Cost Computation
Research Manuscript Mixed-granularity Parallel Coarse-grained Reconfigurable Architecture
Research Manuscript LPCA: Learned MRC Profiling based Cache Allocation for File Storage Systems
Research Manuscript Xplace: An Extremely Fast and Extensible Global Placement Framework
Research Manuscript Adaptive Window-Based Sensor Attack Detection for Cyber-Physical Systems
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Work-in-Progress Poster Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Manuscript NovelRewrite: Node-Level Parallel AIG Rewriting
Work-in-Progress Poster Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Research Manuscript LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
Research Manuscript Do Not Forget the Software: Bare Metal Neural Acceleration is no fun without it.
Research Manuscript LeHDC: Learning-Based Hyperdimensional Computing Classifier
Research Manuscript PHANES: ReRAM-based Photonic Accelerators for Deep Neural Networks
Research Manuscript Floorplanning with Graph Attention
Research Manuscript SS-LRU: A Smart Segmented LRU Caching for Storage System
Work-in-Progress Poster Improving GPU Performance via Coordinated Kernel Slicing and Multi CUDA Streaming
Work-in-Progress Poster Attacking the TimingCamouflage+ Algorithm
Work-in-Progress Poster Logic Locking Based Trojans: A Friend Turns Foe
Engineering Tracks Novel Approach to Early detection of Metastability related issues
Research Panel Heterogeneous 3D or Monolithic 3D, Which Direction to Go?
Engineering Tracks A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Engineering Tracks Novel Approach to Early detection of Metastability related issues
Research Manuscript Using Machine Learning to Optimize Graph Execution on NUMA Machines
Work-in-Progress Poster Automatic Generation of Cell Based structured CIM Macros
Work-in-Progress Poster FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture
Work-in-Progress Poster MuZero-guided Simulated Annealing for Nanometer Circuit Placement
Networking Reception FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Research Manuscript Raven: A Novel Kernel Debugging Tool on RISC-V
Research Manuscript AL-PA: Cross-Device Profiled Side-Channel Attack using Adversarial Learning
Research Manuscript Exploiting Data Locality in Memory for ORAM to Reduce Memory Access Overheads
Research Manuscript Tailor: Removing Redundancy in Memristive Analog Neural Network Accelerators
Research Manuscript Optimizing Quantum Circuit Placement via Machine Learning
Research Manuscript Improving LUT-Based Optimization for ASIC
Work-in-Progress Poster An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Work-in-Progress Poster RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
Research Manuscript Winograd Convolution: A Perspective from Fault Tolerance
Work-in-Progress Poster An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Research Manuscript Precise and Scalable Shared Cache Contention Analysis for WCET Estimation
Research Manuscript Scheduling and Analysis of Real-Time Tasks with Parallel Critical Sections
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Work-in-Progress Poster Addressing Ordering Woes of PCIe with Formal Verification
Engineering Tracks Library Analytics and Library Partitioning [LALP] for PPA Efficiency
Research Manuscript CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs
Networking Reception Hardware-Efficient Stochastic Rounding Unit Design for DNN Training
Work-in-Progress Poster Aging-aware memristor for reliable and energy-efficient Deep Learning Acceleration
Research Manuscript Silicon Validation of LUT-based Logic-Locked IP Cores
Special Session (Research) Trusting the Trust Anchor: Towards Detecting Cross-Layer Vulnerabilities with Hardware Fuzzing
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Research Manuscript Cool Interconnects for Cool Accelerators on Top of Congestion Free Place & Route
Research Manuscript A Defect Tolerance Framework for Improving Yield
Work-in-Progress Poster An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Work-in-Progress Poster RankNAS: A Differential NAS based Auto Rank Search towards Video LSTM Networks on Edge
Research Manuscript GNNIE: GNN Inference Engine with Load-balancing and Graph-specific Caching
Work-in-Progress Poster TrustToken, Trusted SoC solution for Non-Trusted Intellectual Property (IP)s.
Work-in-Progress Poster System-Level Design and Target Agnostic High-Level Optimizations for HLS
Research Manuscript CLIMBER: Defending Phase Change Memory Against Inconsistent Write Attacks
Work-in-Progress Poster An Energy-Efficient Multi-bitwidth Systolic ReRAM Accelerator for NAS Optimized CNN Networks
Research Manuscript O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
Special Session (Research) Large-scale Model-free Feature Selection and Visualization
Special Session (Research) Ubiquitous ML and Security: Can they co-exist?
Research Manuscript BlueSeer: AI-Driven Environment Detection via BLE Scans*
Engineering Tracks Verifying Register Maps with JasperGold: How Formal compares to UVM
Work-in-Progress Poster Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations
Engineering Track Poster Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
Engineering Tracks Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
Engineering Tracks Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios
Engineering Tracks Verifying Register Maps with JasperGold: How Formal compares to UVM
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Engineering Tracks Generation And Selection Of Universally Routable Via Mesh Specifications
Work-in-Progress Poster A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Work-in-Progress Poster HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Research Manuscript Designing Critical Systems with Iterative Automated Safety Analysis
Work-in-Progress Poster SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
Work-in-Progress Poster FPGNN-ATPG: An Efficient Fault Parallel Automatic Test Pattern Generator
Work-in-Progress Poster A Linear Column-Major Capacitance Multiplier based Analog In-Memory Computing Architecture
Work-in-Progress Poster Mentha: Enabling Sparse-Aware Computation on Systolic Arrays
Research Panel What is the Future for Open-Source EDA?
Research Manuscript SEALS: Sensitivity-driven Efficient Approximate Logic Synthesis
Work-in-Progress Poster A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Special Session (Research) Automating Hardware Security Property Generation
Work-in-Progress Poster Quantum Multiple-Valued Decision Diagrams with Linear Transformations
Work-in-Progress Poster Instant Data Sanitization on Multi-Level-Cell NAND Flash Memory
Engineering Tracks Machine Learning Techniques for PDK Development Efficiency
Special Session (Research) Quantum Algorithm Design: A new tool for the design automation of quantum computing circuits
Work-in-Progress Poster System-Level Design and Target Agnostic High-Level Optimizations for HLS
Work-in-Progress Poster LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Research Manuscript Improving LUT-Based Optimization for ASIC
Engineering Track Poster Process Monitoring Blocks - for Monitoring Analog Performance
DAC Pavilion Gladiator Arena Poster Battle A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage
Work-in-Progress Poster Logic Locking Based Trojans: A Friend Turns Foe
Work-in-Progress Poster Addressing Ordering Woes of PCIe with Formal Verification
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript PANORAMA: Divide-and-Conquer Approach for Mapping Complex Loop Kernels on CGRA
Engineering Tracks Ensuring Accurate Crosstalk Analysis using CCS-Noise Liberty Model
Engineering Tracks Maximize GPGPU performance-per-watt across real scenarios with 10x efficient power solution
Engineering Tracks Power solution to maximize performance-per-watt for GPGPU
Work-in-Progress Poster Attacking the TimingCamouflage+ Algorithm
Work-in-Progress Poster A Proposition for Computing System Design Automaticity and Correctness Potential
Work-in-Progress Poster RFR: An STT-MRAM Cache Management Scheme for Retention Failure Reduction
Engineering Track Poster Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
Work-in-Progress Poster Fingerprinting Workloads for Reconfigurable Shared Accelerators
Research Manuscript GNNIE: GNN Inference Engine with Load-balancing and Graph-specific Caching
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Work-in-Progress Poster Accelerating Data Analytics near Memory: A k-NN Search Case Study
Work-in-Progress Poster Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Work-in-Progress Poster AI-Driven Accelerometer-Based Bird Activity Recognition
Work-in-Progress Poster Vector In Memory Architecture for simple and high efficiency computing
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Special Session (Research) A Distributed Approach to Silicon Compilation
Engineering Tracks Enabling a 20B-transistor Chip with Unit Level Timing Abstraction
Work-in-Progress Poster Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations
Research Manuscript Generic Lithography Modeling with Dual-band Optics-Informed Neural Networks
Research Manuscript Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing*
Engineering Track Poster AI-based Neural network approach for performance estimation of complex System-on-Chip
Work-in-Progress Poster Circumventing Machine Learning-Based Attacks to Logic Locking
Engineering Tracks In-design IR drop convergence with Ansys RHSC and SNPS fusion compiler
Research Manuscript ALICE: An Automatic Design Flow for eFPGA Redaction
DAC Pavilion Gladiator Arena Poster Battle Design Timing Effects of Layer-to-Layer Interconnect Skew
Special Session (Research) Secure by Construction: Addressing Security Vulnerabilities Introduced During High-level Synthesis
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Engineering Track Poster AI-based Neural network approach for performance estimation of complex System-on-Chip
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Back-End Design New Directions in Silicon Solutions
Research Manuscript Accelerating and Pruning CNNs for Semantic Segmentation on FPGA
Research Manuscript Efficient Ensembles of Graph Neural Networks
Engineering Tracks RTL Design Security Verification for Resisting Power Side-Channel Analysis
Engineering Tracks Encryption Interoperability with IEEE 1735
Work-in-Progress Poster A Custom Macro Suite for Optimization of Neuromorphic TNN Designs in CMOS
Work-in-Progress Poster Ambient Temperature Estimation using Neural Networks and Device Contextual Information
Networking Reception A Fast and Low-Cost Comparison-Free Sorting Engine with Unary Computing
Work-in-Progress Poster SoC Platform for Heterogeneous Multiple IP Core Evaluation
Engineering Tracks Optimization of hot/cold separation algorithm computation for SSD
Work-in-Progress Poster Display Pixel Layout Design with Deep Reinforcement Learning
Work-in-Progress Poster Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Research Manuscript FHDnn: Communication Efficient and Robust Federated Learning for AIoT Networks
Engineering Tracks SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION
Work-in-Progress Poster HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Research Manuscript A Defect Tolerance Framework for Improving Yield
Research Manuscript How Fast can you go? It is a mad, mad, mad, mad placement world!
Special Session (Research) Unsupervised learning for gate sizing
Special Session (Research) Quantum Algorithm Design: A new tool for the design automation of quantum computing circuits
Work-in-Progress Poster A Coq Framework for More Trustworthy DRAM Controllers
Special Session (Research) mflowgen: A Modular Flow Generator and Ecosystem for Community-Driven Physical Design
Research Manuscript NAX: Neural Architecture and Memristive Xbar based Accelerator Co-design
Work-in-Progress Poster HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Work-in-Progress Poster Adaptive Sparsity-Aware Cloud Offloading for Edge DNN Inference
Special Session (Research) ScaleHLS: a Scalable High-Level Synthesis Framework with Multi-level Transformations and Optimizations
Work-in-Progress Poster AutoPilot: Compute Design Automation for Autonomous Drones
Research Manuscript Hexagons are the Bestagons: Design Automation for Silicon Dangling Bond Logic
Research Manuscript SEALS: Sensitivity-driven Efficient Approximate Logic Synthesis
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
Research Manuscript An In-Memory-Computing Architecture for Recommendation Systems
Special Session (Research) Hammer: A Modular and Reusable Physical Design Flow Tool
Research Manuscript Accelerating DC Circuit Simulation with Reinforcement Learning
Engineering Tracks Learnings from RDC Sign-Off on Low Power SoC
Research Manuscript Orders of Magnitude Acceleration
Research Manuscript Pref-X: A Framework to Reveal Data Prefetching in Commercial In-Order Cores
Research Manuscript Hyperdimensional Hashing: A Robust and Efficient Dynamic Hash Table
Work-in-Progress Poster Automation of Functional Safety and Security Methods for Design and Verification
Work-in-Progress Poster HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
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DAC Pavilion Panel Is Democratization of Chip Design Already Happening?
Back-End Design New Directions in Silicon Solutions
Work-in-Progress Poster A Domain-Specific System-On-Chip Design for Energy Efficient Wearable Edge AI Applications
Research Manuscript Fast and Scalable Human Pose Estimation using mmWave Point Cloud
Research Manuscript TAIM: Ternary Activation In-Memory Computing Hardware with 6T SRAM Array
Work-in-Progress Poster Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Research Manuscript Side Channels go Mainstream !!
Special Session (Research) A Distributed Approach to Silicon Compilation
Research Panel What is the Future for Open-Source EDA?
Work-in-Progress Poster A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Work-in-Progress Poster SoC Platform for Heterogeneous Multiple IP Core Evaluation
Engineering Tracks A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
Research Manuscript Contrastive Quant: Quantization Makes Stronger Contrastive Learning
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Work-in-Progress Poster RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64
Engineering Tracks Thermal Aware Memory Controller Design with Chip Package System Simulation
Work-in-Progress Poster Implementing Efficient, Precise N-bit Operations of TFHE on Commodity CPU-FPGA
Work-in-Progress Poster Leveraging Layout-based Effects for Locking Analog ICs
Engineering Tracks Low Power Classes as extension to UVM Package Library
Special Session (Research) Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
Engineering Tracks Smart Strategy to analyze CDC Violation related to IPs Interaction at SoC
Work-in-Progress Poster Agile: A Collaborative Air-ground IoT Edge Framework for Sustainable Remote Monitoring
Research Manuscript VirTEE: A Full Backward-Compatible TEE with Native Live Migration and Secure I/O
Research Manuscript A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
Research Manuscript ADEPT: Automatic Differentiable DEsign of Photonic Tensor Cores
Research Manuscript QOC: Quantum On-Chip Training with Parameter Shift and Gradient Pruning
Work-in-Progress Poster Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Research Manuscript GNN-based Concentration Prediction for Random Microfluidic Mixers
Engineering Tracks Smart Strategy to analyze CDC Violation related to IPs Interaction at SoC
Research Manuscript AI and ML on next generation computing platforms
Engineering Track Poster FSDB based Self-Gating technique for Power saving and FEV Verification approaches
Engineering Tracks PostMask functional ECO Implementation flow using Programmable cells
Engineering Tracks Minimum repeater addition ECOs for power efficient designs
Engineering Tracks Cell EM aware Design Optimization
Engineering Track Poster Formal based Automation Framework to Verify Coherent Connectivity of Multi-instance IPs
Research Manuscript FaSe: Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks
Research Manuscript HWST128: Complete Memory Safety Accelerator on RISC-V with Metadata Compression
Research Manuscript Security of AI and AI for security
Engineering Tracks Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios
Engineering Tracks SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION
Engineering Tracks Learnings from RDC Sign-Off on Low Power SoC
Engineering Tracks Workflow Automation for SoC Performance Verification
Engineering Tracks Automatic Debug Knowledge Sharing Platform in SOC Verification
Engineering Tracks Machine Learning Based Abnormal Simulation Detector in SoC Verification
Engineering Tracks Design Verification for Virtual Prototype Exploiting UVM
Work-in-Progress Poster Accelerating Data Analytics near Memory: A k-NN Search Case Study
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Tracks New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
Engineering Tracks On-Chip PDN-Aware Simulation Methodology with RC Network Reduction
Research Manuscript A Fast and Scalable Qubit-Mapping Method for NoisyIntermediate-Scale Quantum Computers
Work-in-Progress Poster Graph Partitioning Approach for Fast Quantum Circuit Simulation
Research Manuscript Effective Zero Compression on ReRAM-based Sparse DNN Accelerators
Engineering Tracks Extracting Source of Unknown Values in Transistor-level Logic Simulation
Engineering Tracks Fast Design Space Exploration using RTL Architect for DRAM Designs
DAC Pavilion Gladiator Arena Poster Battle A unified IP QA methodology to improve validation coverage and throughput
Engineering Track Poster Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement