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Organization

Peking University
Presenters
Zizheng Guo
Ru Huang
Liancheng Jia
Xingchen Li
Yun Liang
Yibo Lin
Jing Mai
Yibai Meng
Guangyu Sun
Runsheng Wang
Bonan Yan
Zhihang Yuan
Zuodong Zhang
Presentations
Research Manuscript
A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction
EDA
Timing and Low Power Design
Research Manuscript
ASTERS: Adaptable Threshold Spike-timing Neuromorphic Design with Twin-Column ReRAM Synapses
Design
Emerging Models of Computation
Research Manuscript
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Application-based DVAFS
EDA
Manufacturing Test and Reliability
Research Manuscript
Differentiable Timing Driven Global Placement
EDA
Physical Design and Verification, Lithography and DFM
Research Manuscript
EMS: Efficient Memory Subsystem Synthesis for Spatial Accelerators
AI
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
EDA
In-Package and On-Chip Communication and Networks-on-Chip
Physical Design and Verification, Lithography and DFM
Research Manuscript
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity and Clock Feasibility
Design
Physical Design and Verification, Lithography and DFM
Research Manuscript
Tailor: Removing Redundancy in Memristive Analog Neural Network Accelerators
Design
AI/ML Design: Circuits and Architecture
Digital and Analog Circuits