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Organization

The Chinese University of Hong Kong
Presenters
Chen BAI
Jingsong Chen
Tinghuan Chen
Bangqi Fu
Hao Geng
Zhuolun He
Pheng Ann Heng
Tsung-Yi Ho
Bentian Jiang
Sadaf Khan
Chi Ngai Leung
Min Li
Shiju Lin
Jinwei Liu
Lixin LIU
Tianji Liu
Zhengyuan Shi
QI SUN
Ho Ming Tsui
Bowen Wang
Qijing Wang
Ziyi Wang
Martin Wong
Qiang Xu
Ming-Chang Yang
Evangeline Young
Bei Yu
Xinshi Zang
Xiaopeng Zhang
Xinyun Zhang
Yuxuan Zhao
Presentations
Research Manuscript
A Fast Parameter Tuning Framework via Transfer Learning and Multi-objective Bayesian Optimization
EDA
System-on-Chip Design Methodology
Research Manuscript
A2-ILT: GPU Accelerated ILT with Spatial Attention Mechanism
EDA
Physical Design and Verification, Lithography and DFM
Networking Reception
Work-in-Progress Poster
Aging-aware Critical Path Selection via Graph Attentional Networks
Research Manuscript
DeepGate: Learning Neural Representations of Logic Gates*
AI
ML Algorithms and Applications
Research Manuscript
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform
Design
SoC, Heterogeneous, and Reconfigurable Architectures
Research Manuscript
Functionality Matters in Netlist Representation Learning
AI
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
GNN-based Concentration Prediction for Random Microfluidic Mixers
Design
Emerging Device Technologies
Research Manuscript
GTuner: Tuning DNN Computations on GPU via Graph Attention Network
AI
Embedded Systems
RISC-V
Embedded Software
Research Manuscript
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction
EDA
In-Package and On-Chip Communication and Networks-on-Chip
Physical Design and Verification, Lithography and DFM
Research Manuscript
NovelRewrite: Node-Level Parallel AIG Rewriting
EDA
RTL/Logic Level and High-level Synthesis
Research Manuscript
Partition and Place Finite Element Model on Wafer Scale Engine
Design
Physical Design and Verification, Lithography and DFM
Research Manuscript
PPATuner: Pareto-driven Tool Parameter Auto-tuning in Physical Design via Gaussian Process Transfer Learning
EDA
Timing and Low Power Design
Research Manuscript
SMART: On Simultaneously MArching RaceTracks to Improve the Performance of RaceTrack-based Main Memory
Embedded Systems
Embedded Memory, Storage and Networking
Research Manuscript
Xplace: An Extremely Fast and Extensible Global Placement Framework
EDA
Physical Design and Verification, Lithography and DFM