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Organization

Intel
Presenters
Mohamed Abdel-Moneum
Goutami Aenuganti
Krunal Agrawal
Shreyansh Agrawal
Chandrahas Alla
Dipankar Arya
Mahesh Baghel
Rakshit Bazaz
Greg Bradford
Bob Brennan
Steven Burns
Lekshmi C
NIjesh C
Rossario Cammarota
Luis Campos
Erik Carstensen
Thirumala Chakravarthy
Amaresh Chellapilla
Pasquale Cocchini
Vivek De
Sabyasachi Dey
Suhas DS
Shrisagar Dwivedi
Nagi Reddy Emani
Jakob Engblom
Jason Fung
Tapan Ganpule
Shrikrishna Gawade
Praveen Ghagare
Santosh Ghosh
Rahul Goyal
Raghav Gupta
Shivangi Gupta
Shankar Hemmady
Jeffrey Hicks
Jennifer Huffstetler
Aman Jain
Anshul Jain
Hemant Jain
Amol Joshi
Sanjana Kale
Mei War Kan
Basavaraj Kanthi
Anil Kawediya
Anmol Khatri
Donald Kline, Jr
sudarshanam kommanaboyina
Sasi koney
Max Korbel
Bhuoender Kumar
Manish Kumar
Raghavan Kumar
Madan Lal
Zhi Feng Lee
Sonia Leon
Carlston Lim
Shubham Lunawat
Achutha KiranKumar V M
Divya M
Joydeep Maitra
Amartya Mazumdar
Noel Menezes
Ashutosh Mishra
Vedprakash Mishra
Zafar Mohammad
Jebin Mohandas
Harshal Mumbaikar
Manoj Munigala
Usha Muruli
Madhusudhan N
Shaman Narayana
Suriya Natarajan
Eriko Nurvitadhi
Sidarth Panda
Shiven Pandya
Bhushan Parikh
Ravi Pillarisetty
Shavindra Premarante
Raghunandana R
Srivatsa rangachar srinivasa
Srivatsa rangachar srinivasa
Bindu Rao
Senthil Ravi
Monika Rawat
Sayak Ray
Purushotham Reddy
Suhas Reddy
Kenneth Roe
Leila Sabeti
Deepmala Sachan
Gopalakrishnan Sadagopan
Sourav Saha
Pandithurai Sangaiyah
Albert Schmitz
Alina Sebastian
Mithil Shah
Vinit Shenoy
Guneet Singh
Surinder Sood
Vineet Sreekumar
Archanna Srinivasan
Zhi Sheng Teh
Carlos Tokunaga
Parag Upadhyay
Suresh Vasu
Nithin Venkatesh
Sumit Wadkar
Jian Zhong Wang
Wei Wu
Xin-Chuan Wu
Raj Yadav
Jin Yang
Zhenkun Yang
Pavan Yeluri
Session Chairs
Navid Farazmand
Ankit Gopani
Steven Hsu
Presentations
Engineering Track Poster
Engineering Tracks
4G/5G Encoder-Decoder IP Use Cases and Performance Validation in Emulation and Post Silicon using Portable Stimulus Standard’s HSI
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Research Manuscript
A Defect Tolerance Framework for Improving Yield
EDA
Manufacturing Test and Reliability
Engineering Track Poster
Engineering Tracks
A Dynamic approach towards NOC Performance Verification in Pre-Silicon and Overcome the traditional Overheads
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
Engineering Tracks
A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage
Back-End Design
Embedded Systems
Front-End Design
IP
Networking Reception
Work-in-Progress Poster
A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange
Special Session (Research)
Accelerator Design with Decoupled Hardware Customizations: Benefits and Challenges
EDA
Research Manuscript
Adaptive Neural Recovery for Highly Robust Brain-like Representation
AI
AI/ML Security/Privacy
Networking Reception
Work-in-Progress Poster
Addressing Ordering Woes of PCIe with Formal Verification
Back-End Design
Engineering Tracks
Advanced Comprehensive Debug methodology to accelerate SOC timing convergence
Back-End Design
Engineering Track Poster
Engineering Tracks
AI assisted smart analysis (AISA) for system level issue localization in post silicon validation
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
AI-based Neural network approach for performance estimation of complex System-on-Chip
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Automated Timing Degradation Recovery in Incremental Tape-Out of High-Speed CPU Design
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Embedded Systems and Software
Engineering Tracks
Automatic Checkpoint Support in the Device Modeling Language (DML)
Embedded Systems
RISC-V
Research Panel
Automating Analog Layout - Has the time finally come?
AI
EDA
Special Session (Research)
Automating Hardware Security Property Generation
Security
Engineering Track Poster
Engineering Tracks
Compiler Approach for Automating Die2Die Trans-receiver HIP Placement for 3D-IC Design
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Converging the “World’s Densest” PNR design on TSMC N5P - Beating Custom SRAM transistor densities in synthesized Place & Routed Design
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
IP
Creating Robust EDA and IP Ecosystems to Strengthen the Global Semiconductor Supply Chain
IP
Research Panel
Cryogenic Computing, Super Cool or Not?
Design
Embedded Systems and Software
Engineering Tracks
Design Considerations for Embedded at the Edge
Embedded Systems
Engineering Track Poster
Engineering Tracks
Efficient stimulus generation techniques for a UVM TB
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Networking Reception
Work-in-Progress Poster
Equivalence Checking for Agile Hardware Design
Engineering Tracks
Front-End Design
Formal verification contract based micro architectural analysis of Server SoC's
Front-End Design
Engineering Track Poster
Engineering Tracks
Formal Verification of Deep Neural Networks in Hardware
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
FSDB based Self-Gating technique for Power saving and FEV Verification approaches
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Research Panel
Heterogeneous 3D or Monolithic 3D, Which Direction to Go?
EDA
DAC Pavilion Panel
How Robust is Your Hardware Security Program?
Security
Networking Reception
Work-in-Progress Poster
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Back-End Design
Engineering Tracks
I/O Constraints Optimization
Back-End Design
Research Manuscript
Improving Compute In-Memory ECC Reliability with Successive Correction
Design
Emerging Device Technologies
Engineering Track Poster
Engineering Tracks
In-design IR drop convergence with Ansys RHSC and SNPS fusion compiler
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
Front-End Design
Innovative Low Power UPF GENERATION and HIERARCHICAL MODELING OF Custom blocks
Front-End Design
Back-End Design
Engineering Tracks
Intelligent Floorplanning (IFP)
AI
Back-End Design
Engineering Track Poster
Engineering Tracks
Left Shift of Multi-Cycle Paths and False Paths Signoff By Formal and Dynamic Simulation Methodologies with significant ROI
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Library Analytics and Library Partitioning [LALP] for PPA Efficiency
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Low Power Verification Challenges of Hierarchical UPF in Discrete Graphics SoC Design
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Minimum repeater addition ECOs for power efficient designs
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Mitigation of Soft-Errors in Storage Elements through Layout and Circuit Design Techniques
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Networking Reception
Work-in-Progress Poster
Novel ML based Reconfigurable Macro Placement for SoC Design
Research Manuscript
O'Clock: Lock the Clock via Clock-gating for SoC IP Protection
AI
Security
Hardware Security: Attack and Defense
Hardware Security: Primitives, Architecture, Design & Test
Tech Talk
Open Architectures to Accelerate Industry Growth
Engineering Track Poster
Engineering Tracks
PostMask functional ECO Implementation flow using Programmable cells
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Back-End Design
Engineering Tracks
Prototyping and verification of Power Delivery network for a Foveros 3DIC design.
Back-End Design
Back-End Design
Engineering Tracks
Pushing Boundaries - Challenges for Next-Generation Chip Design
Back-End Design
Back-End Design
Engineering Tracks
Python based Standalone toolkit for Standard Cell library & RTL Power Statistical Analysis
Back-End Design
Engineering Track Poster
Engineering Tracks
ROHD: The Rapid Open Hardware Development Framework
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Back-End Design
Embedded Systems and Software
Engineering Tracks
Front-End Design
IP
Silent Errors from Computing Hardware: A Cambrian Explosion in New Innovations is Dead Ahead
Back-End Design
Embedded Systems
Front-End Design
IP
Workshop
Software Stack Design for Quantum Computing
Design
Quantum Computing
Engineering Tracks
Front-End Design
System and method to improve RTL quality by using backend tools flows and methodology for RTL Handoff
AI
Cloud
Front-End Design
Engineering Track Poster
Engineering Tracks
SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Back-End Design
Engineering Tracks
The Hardware/Software Nexus in Chip Design
Back-End Design
Engineering Tracks
Front-End Design
UPF Restructuring Flow Based On Power Promotion and Demotion Capabilities
Front-End Design
Networking Reception
Work-in-Progress Poster
WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems
DAC Pavilion Panel
What can EDA and the Electronics Ecosystem Do for Greener Electronics to Save the Planet?
EDA
Research Panel
What is the Future for Open-Source EDA?
EDA
Sessions
Engineering Tracks
Front-End Design
New Developments in Security Verification and Controlling Unpredictable Behavior
Front-End Design
Engineering Tracks
IP
The interdependence between ML/AI and chip design automation
IP
Research Manuscript
Cost-Efficient Analog and Stochastic Computing Techniques for Deep Learning
Design
AI/ML Design: Circuits and Architecture
Digital and Analog Circuits