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Organization

STMicroelectronics
Presenters
Atul Bhargava
Edoardo Bollea
Anubhuti Chopra
Anil Dwivedi
Anil Kumar Dwivedi
Frederic Esteban
Jean-Arnaud Francois
Harsh Garg
Gaurav Goel
Rohit Goel
Devendra Gupta
Ashish Kumar
Rahul Kumar
Alessandro Locardi
Andrea Lopinto
Geeta Madan
VENY MAHAJAN
Priya Meharde
ANAND MISHRA
Mitu Mittal
Lippika Parwani
mihir pratap
Davide Sanalitro
Geetanjali Sharma
Bhupendra Singh
Rajeev Singh
Natish Singla
natish Singla
Saurabh Srivastava
saurabh srivastava
Priya Talwar
David Vincenzoni
Presentations
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
Engineering Tracks
A unified IP QA methodology to improve validation coverage and throughput
Back-End Design
Embedded Systems
Front-End Design
IP
Back-End Design
Engineering Tracks
Characterization Challenges in System Level IO Interface
Back-End Design
Engineering Track Poster
Engineering Tracks
Design Intent Driven Analog Routing Methodology
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Ensuring Accurate Crosstalk Analysis using CCS-Noise Liberty Model
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Integrating Liberty model validation, analysis, and visualization as part of library design and characterization
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
IP
Memory Read Yield Estimation Using High Sigma Monte Carlo
AI
IP
Engineering Tracks
Front-End Design
Novel Approach to Early detection of Metastability related issues
Front-End Design
Engineering Track Poster
Engineering Tracks
On-Chip embedded sensor in 18nm technology to monitor the effects of process variations on standard cells logic and interconnect delays
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Process Monitoring Blocks - for Monitoring Analog Performance
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
SDR (Simulation-Driven Routing): A Solution to Get Electromigration Compliant Routing
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Streamlined Solution for CAD Views Generation & Validation of AMS IP for SoC Enablement
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Technology co-optimization to mitigate the technology impact of context-based timing in standard Cell library
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Using Formal Verification Signoff for Digital IP
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
IP
Verifying I/O Designs Using Symbolic Simulation to Increase Design and Model Robustness
AI
IP
Engineering Tracks
Front-End Design
Verifying Register Maps with JasperGold: How Formal compares to UVM
Front-End Design