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Organization

Synopsys
Presenters
Rob Aitken
Rob Aitken
Sampath Amarasinghe
Luca Amaru
Asheesh Baghel
Ankush Bagotra
Bari Biswas
Mayur Bubna
Jian-Feng Chen
Hari Cherupalli
Olivier Coudert
Sabya Das
Li Ding
Amit Goldie
Varun Gunnala
Len Hsu
Li-Chung Hsu
Duc Huynh
Jinmo Jung
Himanshu Kathuria
Jamil Kawa
Khader Khader Abdel-Hafez
KH Kim
YongJoon Kim
Donghyun Lee
Tong Liu
Jiong Luo
Sandeep Mehndiratta
ayhan mutlu
Sashi Obilisetty
Sashi Oblisetty
Min Pan
Vivek Panure
Vinicius Possani
Radhika Shankar
Ruijing Shen
Rakesh Shenoy
Moninder Singh
Dongli Song
Weikai Sun
Patrick Vuillod
Joe R Walston
Yervant Zorian
Session Chairs
Maheshwar Chandrasekar
Sabya Das
Karthi Duraisamy
Shahin Golshan
Siddhartha Nath
Sashi Obilisetty
Deepashree Sengupta
Sripada Subramanyam
Presentations
Engineering Track Poster
Engineering Tracks
A High-Accuracy Voltage-Aware-Timing Solution for HPC Design
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Research Manuscript
A scalable symbolic simulation tool for low power embedded systems
Embedded Systems
RISC-V
Embedded System Design Methodologies
Time-Critical System Design
Engineering Track Poster
Engineering Tracks
Automated Timing-aware Dynamic Voltage Drop ECO
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Research Panel
Automating Analog Layout - Has the time finally come?
AI
EDA
Engineering Track Poster
Engineering Tracks
Cell EM aware Design Optimization
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
IP
Creating Robust EDA and IP Ecosystems to Strengthen the Global Semiconductor Supply Chain
IP
Research Panel
Cryogenic Computing, Super Cool or Not?
Design
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
Engineering Tracks
Design Timing Effects of Layer-to-Layer Interconnect Skew
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
FPopt: ML-Based Chip Floorplan Optimization
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Research Manuscript
Improving LUT-Based Optimization for ASIC
EDA
RTL/Logic Level and High-level Synthesis
SKYTalk
It’s Getting Cloudy Out There
Cloud
Design
Back-End Design
Engineering Tracks
Machine Learning and EDA: The Productivity Cycle
AI
Back-End Design
Engineering Tracks
IP
Memory Read Yield Estimation Using High Sigma Monte Carlo
AI
IP
Networking Reception
Work-in-Progress Poster
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Back-End Design
Engineering Tracks
New Directions in Silicon Solutions
Back-End Design
Engineering Tracks
IP
Open Source Hardware to enable faster TTR
IP
Engineering Track Poster
Engineering Tracks
Static Timing and Power Analysis with Process Space Exploration
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Research Panel
Tackling Trust through Verification and Assessment: Wishful Thinking or Inevitable Reality?
Security
Back-End Design
Engineering Tracks
The Hardware/Software Nexus in Chip Design
Back-End Design
Engineering Tracks
IP
Verifying I/O Designs Using Symbolic Simulation to Increase Design and Model Robustness
AI
IP
Back-End Design
Engineering Tracks
VFopt: ML-Based Optimization Voltage/Frequency Exploration System
Back-End Design
Research Panel
What is the role of the EDA community in future life science breakthroughs?
EDA
DAC Pavilion Panel
Women in Engineering: Real Advice for Today’s Female Engineers
Sessions
Back-End Design
Engineering Tracks
The Hardware/Software Nexus in Chip Design
Back-End Design
Engineering Tracks
IP
Open Source Hardware to enable faster TTR
IP
Research Manuscript
Machine Learning for Synthesis and Synthesis for Machine Learning
AI
EDA
RTL/Logic Level and High-level Synthesis
Back-End Design
Engineering Tracks
New Directions in Silicon Solutions
Back-End Design
Research Manuscript
How Fast can you go? It is a mad, mad, mad, mad placement world!
EDA
Physical Design and Verification, Lithography and DFM
Research Manuscript
Keep moving up and looking sideways with verification boosters!
EDA
Design Verification and Validation
Research Manuscript
Timing-Critical Design
Embedded Systems
Time-Critical System Design
Research Manuscript
So You Want a Better Design? Go with Faster Timing and Lower Power Please!
EDA
Timing and Low Power Design