Organization

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Samsung Electronics

Presenters

Jieun Ahn

Presentations

Networking Reception

Work-in-Progress Poster

A Page-mapping Consistency Protecting Method for Soft Error Damage in Flash-based Storage

Networking Reception

Work-in-Progress Poster

Ambient Temperature Estimation using Neural Networks and Device Contextual Information

Engineering Track Poster

Engineering Tracks

Automated Timing-aware Dynamic Voltage Drop ECO

Engineering Tracks

Front-End Design

Automatic Debug Knowledge Sharing Platform in SOC Verification

Engineering Track Poster

Engineering Tracks

Back End of Line Process-aware Static Timing Analysis

Engineering Track Poster

Engineering Tracks

Cell EM aware Design Optimization

Engineering Track Poster

Engineering Tracks

Clock Spine Automation for Clock Latency and Turn-Around-Time Reduction

Engineering Track Poster

Engineering Tracks

Clustering Characterization Condition for Multi-bit Cell

Back-End Design

Engineering Tracks

Design Rule Decision Methodology For Balancing Process Limit and Routability Improvement

Embedded Systems and Software

Engineering Tracks

Design Verification for Virtual Prototype Exploiting UVM

Engineering Track Poster

Engineering Tracks

Dynamic CDC Verification with Enhanced Jitter Modeling in Synchronizers

Engineering Track Poster

Engineering Tracks

Efficient Custom Logic P&R Flow using Virtual Hierarchy

Engineering Track Poster

Engineering Tracks

Efficient read/write turn-around policy of LPDDR5 memory controller

Engineering Track Poster

Engineering Tracks

Enhancing Silicon Screening Using Optimized Clustering-Based SDD Vector

Engineering Tracks

Front-End Design

Extracting Source of Unknown Values in Transistor-level Logic Simulation

Engineering Track Poster

Engineering Tracks

Fast Design Space Exploration using RTL Architect for DRAM Designs

Engineering Track Poster

Engineering Tracks

FPopt: ML-Based Chip Floorplan Optimization

Back-End Design

Engineering Tracks

Implementing QDI Design with Conventional Synchronous Design Flow: A Case of Long Distance Interconnect across Voltage Domain

Engineering Track Poster

Engineering Tracks

Learnings from RDC Sign-Off on Low Power SoC

Engineering Tracks

Front-End Design

Machine Learning Based Abnormal Simulation Detector in SoC Verification

Engineering Tracks

Machine Learning-based BER Estimation in Receiver IBIS-AMI Modeling

DAC Pavilion Gladiator Arena Poster Battle

Engineering Track Poster

Engineering Tracks

Minimize Power Consumption with A Novel Power ECO Flow

Special Session (Research)

MRAM In - memory Computing Crossbar Array

Engineering Track Poster

Engineering Tracks

New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design

Research Manuscript

NN-LUT: Neural Approximation of Non-Linear Operations for Efficient Transformer Inference

Back-End Design

Engineering Tracks

On-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis using STA native timing engine

Engineering Track Poster

Engineering Tracks

On-Chip PDN-Aware Simulation Methodology with RC Network Reduction

Embedded Systems and Software

Engineering Tracks

Optimization of hot/cold separation algorithm computation for SSD

Back-End Design

Engineering Tracks

Performance-driven Multi-bit Optimization Flow

Engineering Track Poster

Engineering Tracks

ProtoLint: Protocol- and IP-Aware Lint for RTL Integration

Engineering Tracks

Shared Virtual Output Queuing: Maximizing NoC Switch Utilization

Engineering Track Poster

Engineering Tracks

Static Timing and Power Analysis with Process Space Exploration

Engineering Track Poster

Engineering Tracks

The Introduction and Best Practices of Semiconductor Chip Design Model on the Cloud

Back-End Design

Engineering Tracks

Thermal-aware Power and Performance Simulator

Networking Reception

Work-in-Progress Poster

Transformed Data and Faster-SPDZ : Techniques for Privacy-Preserving Deep Learning in Real-World Applications

Back-End Design

Engineering Tracks

VFopt: ML-Based Optimization Voltage/Frequency Exploration System

Engineering Track Poster

Engineering Tracks

Workflow Automation for SoC Performance Verification