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Organization

National Taiwan University
Presenters
Kevin Kai-Chun Chang
Yao-Wen Chang
Chun Chen
Kuan-Cheng Chen
Yen-Ting Chen
Chun-Yao Chiang
Tao Chou
Chia-Che Chung
Chao-Ho Hsieh
Cheng-Yun Hsieh
Jhih-Wei Hsu
Yu-Ling Hsu
Bo-Wei Huang
Chiao-Shan Jhang
Iris Hui-Ru Jiang
Jie-Hong Roland Jiang
James Li
Chung-Wei Lin
Hsin-Cheng Lin
Wei-Chen Lin
C. W. Liu
Yu-Sheng Lu
Szu-Ru Nie
Yuan-Hung Tsai
Chia-Jung Tsen
Wei-Hsiang Tseng
Cheng-Yuan Wang
Ren-Chu Wang
Chun-Yu Wei
Presentations
Research Manuscript
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits
Design
Quantum Computing
Research Manuscript
Accurate BDD-based Unitary Operator Manipulation for Scalable and Robust Quantum Circuit Verification
Design
Quantum Computing
Research Manuscript
CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs
Design
Physical Design and Verification, Lithography and DFM
Late Breaking Results Poster
Networking Reception
Flexible Chip Placement via Reinforcement Learning
Research Manuscript
High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints
Design
Physical Design and Verification, Lithography and DFM
Networking Reception
Work-in-Progress Poster
ML-Assisted Vmin Binning with Multiple Guard Bands for Low Power Consumption
Networking Reception
Work-in-Progress Poster
Physics-Consistent Thermal SPICE and Multi-Correlated Recurrent Neural Networks to Simulate Sophisticated FinFET Circuitry
Late Breaking Results Poster
Networking Reception
Subgraph Matching Based Reference Placement for PCB Designs
Workshop
The Fifth International Workshop on Design Automation for Cyber-Physical Systems (DACPS)
Embedded Systems
Research Manuscript
Thermal-aware Optical-electrical Routing Codesign for On-Chip Signal Communications
EDA
In-Package and On-Chip Communication and Networks-on-Chip
Physical Design and Verification, Lithography and DFM
Research Manuscript
Timing Macro Modeling with Graph Neural Networks
EDA
Timing and Low Power Design
Research Manuscript
Y-architecture-based Flip-Chip Routing with Dynamic Programming-based Bend Minimization
EDA
Physical Design and Verification, Lithography and DFM