Close
 

Organization

Texas Instruments
Presenters
Lakshmanan Balasubramanian
Rakesh Bansal
Frank Cano
Avinash Chaudhary
Sriraj Chellappan
Stefan Dannenberger
Einar Ellingsen
Shalini Eswaran
Anand G
Saravanan G
Somesh Gode
Otis Gorley
Madhusudhan Gurram
Shivani Jayakumar
Sagar Jogur
Shuchita Kaila
Khyati Kiyawat
Mikael Kromer
Pavan Kumar Kulkarni
Gopika Kumar
Narava Kumar
Gaurav Kumar Varshney
Guha Lakshmanan
Swathy Lal
Shashank Madineni
Harish Maruthiyodan
Arif Mohammed
Ashwini Padoor
Vinod Paparaju
Abhinav Parashar
Venkatraman Ramakrishnan
Gokul Sabada
Siddharth Sarin
Sooraj Sekhar
Malav Shah
Parth Shah
Tapsir Shaikh
Ruchi Shankar
Abhinandan Sharma
Harsh Sharma
Shimoli Shinde
Malav Shrikant Shah
Rajeev Suvarna
Sangram Thopte
Devanathan Varadarajan
Gaurav Varshney
Presentations
Engineering Tracks
Front-End Design
A Novel Analog Centric Automated Verification Methodology Driven by State Diagram Approach
Front-End Design
Back-End Design
Engineering Tracks
An area and test-time efficient in-field memory test framework with tunable guard bands
Back-End Design
Engineering Track Poster
Engineering Tracks
Efficient Low Power Isolation Handling for Pre-Silicon Emulation
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Formal based Automation Framework to Verify Coherent Connectivity of Multi-instance IPs
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
Front-End Design
Fully Automated Modular Method for Comprehensive Low Power Simulation Coverage
Front-End Design
Engineering Track Poster
Engineering Tracks
Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Back-End Design
Engineering Tracks
Quick & Efficient Extraction of Library Pessimism: Enabler for Faster Hold Timing Closure
Back-End Design
Engineering Track Poster
Engineering Tracks
Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
Front-End Design
Smart Comprehensive Automation Frameworks to Resolve the Mainstream Microcontroller SOC Design Challenges
AI
Cloud
Front-End Design
Embedded Systems and Software
Engineering Tracks
Specification driven automation of SoC RTL integration using IP-XACT
Embedded Systems
RISC-V