Close
 

Organization

Siemens EDA
Presenters
Michael Buehler-Garcia
Lionel Couder
Greg Davis
Tina Durgia
Matthieu fillaud
Fady Fouad
Lee Harrison
Karen Henderson
Smitha Kamathi
Mathilde Karsenti
Ivan Kissiov
Russell Klein
Gurpreet Lamba
Joe LeBritton
Amy Pitman
Sadhvi Praveen
Bryan Ramirez
khaled Salah
Hossam Sarhan
Joseph Sawicki
Mike Sheinin
Austin Shirley
Valeriy Sukharev
Wei Tan
Wei-Lii Tan
Pradeep Thiagarajan
Sumit Vishwakarma
Florian Wilde
Jeff Wilson
jeffery Wilson
Presentations
Engineering Tracks
IP
A hierarchical and tractable Mixed Signal verification methodology for first-generation Analog AI Processors
AI
IP
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
Engineering Tracks
A unified IP QA methodology to improve validation coverage and throughput
Back-End Design
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Automated DCAP and filler cell insertion with embedded Design for Inspection (DFI) Sensors
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
SKYTalk
Canceled: Delivering “Smarter” Faster: The Future of EDA & AI
AI
EDA
Back-End Design
Engineering Tracks
Characterization Challenges in System Level IO Interface
Back-End Design
Engineering Track Poster
Engineering Tracks
Chatbot as a Virtual Assistant to Retrieve Information from Datasheets
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Tracks
IP
Creating Robust EDA and IP Ecosystems to Strengthen the Global Semiconductor Supply Chain
IP
Engineering Tracks
IP
Design for Manufacturability (DFM) for Analog IP
AI
IP
Engineering Tracks
Front-End Design
Digital Twin Reimagined - One Model To Rule Them All ?
Front-End Design
Engineering Tracks
IP
Efficient use of on-line LogicBIST to achieve ASIL B in a GPU IP
IP
Back-End Design
Engineering Tracks
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-chip Power Grids
Back-End Design
Engineering Tracks
IP
Frequency synthesizers with a purpose in advanced process technologies
AI
IP
Tutorial
Hardware/Software Co-design with High-Level Synthesis
Design
Engineering Track Poster
Engineering Tracks
Improving Power Grid IR drop with an automated layout enhancement flow
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Engineering Track Poster
Engineering Tracks
Integrating Liberty model validation, analysis, and visualization as part of library design and characterization
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
Back-End Design
Engineering Tracks
Machine Learning and EDA: The Productivity Cycle
AI
Back-End Design
Engineering Tracks
IP
Variation-Aware Design Verification For Automotive Semiconductor IP
IP
Networking Reception
Work-in-Progress Poster
What Helper Data Really Leaks: A Practical Approach to Estimate the Min-Entropy in PUFs Using Their Response Mass Function