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Organization

University of Southern California
Presenters
Peter Beerel
Jatin Bollareddy
Dake Chen
Mike Chen
Subhajit Dutta Chowdhury
Yinghua Hu
Xi Li
Mustafa Munir
Pierluigi Nuzzo
Shiyu Su
Yifeng Xiao
Kaixin Yang
Qiaochu Zhang
Xuan Zhou
Presentations
Research Manuscript
A Cost-Efficient Fully Synthesizable Stochastic Time-to-Digital Converter Design Based on Integral Nonlinearity Scrambling
Design
AI/ML Design: Circuits and Architecture
Digital and Analog Circuits
Networking Reception
Work-in-Progress Poster
Circumventing Machine Learning-Based Attacks to Logic Locking
Networking Reception
Work-in-Progress Poster
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic
Late Breaking Results Poster
Networking Reception
Subgraph Matching Based Reference Placement for PCB Designs
Networking Reception
Work-in-Progress Poster
Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP
Workshop
Workshop on Design Automation for the Certification of Autonomous Systems (DAC-AS)
AI
Autonomous Systems