Power Aware Scan Structure Planner
TimeMonday, July 11th2:30pm - 2:45pm PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Back-End Design
DescriptionIn advanced process, scan testing is suffering from IR issue due to huge design scale and IR analysis tool's capability, especially for AI/HPC design. It takes long period to validate scan structure even if some power aware scan methodology was developed to solve power/IR issue while sometimes designer sacrificed the quality to meet target schedule. This work provides a planner to shorten time required to validate scan structure plan based on bump current modeling. Design fixing and ATPG constraint guidance on power aware scan methodology will be provided if critical region exists in the design.