Performance-driven Multi-bit Optimization Flow
TimeMonday, July 11th11:30am - 11:45am PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Back-End Design
DescriptionConventional MBIT flow focuses on maximizing MBIT ratio, and therefore it is not appropriate for high-speed block because of MBIT speed degradation. The proposed flow can improve frequency by using the following three knobs: ① tightening slack threshold for MBIT merging, ② MBIT mapping inferring RTL bus architecture and ③ splitting MBIT with target slack. Experimental results show 9.6% frequency gain with 3.4% energy deterioration on average compared to conventional MBIT flow. Total MBIT ratio, critical MBIT path ratio and average top300 D-Q delay are meaningfully decreased which are key points for frequency improvement. For future work, we are constantly discussing this proposal with EDA to develop in-build MBIT solution for high-speed block.