Speeding-up Design Closure with Accurate Statistical Timing Macro-models
TimeMonday, July 11th10:30am - 10:45am PDT
Location2008, Level 2
DescriptionTiming macro-models have been backbone in enabling hierarchical chip design and timing closure. These are compact models generated out of a design analysis run that captures key timing information, reproducible at the next level of hierarchy where this macro-model is instantiated and used. These allow for efficient logic re-use as well. A PD/timing engineer owning a set of designs uses EDA tools to generate the models, perform automated model verification and promote the model for use. Any delay or roadblock in this process dramatically reduces the productivity especially towards tail end of design cycle. There has been work in the past to generate accurate and efficient macro-models even in statistical static timing analysis framework. To address model accuracy and mismatch issue for various reasons described in the article, novel technique is proposed that also improves overall model quality upon evaluation. Benefits rise from enhancing finite-difference technique of model statistical evaluation. This resulted in consistent improvement across the space, up to 10-15ps on 5GHz+ processor designs. Another key benefit is designer productivity enhancement where macro-model verification does not encounter mismatches thus saving resource spent to debug issue, fix and rerun. IBM's POWER and Z chip methodologies leverage this technique implemented in EinsTimer, IBM's flagship timing analysis engine.