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Presentation

Advanced Comprehensive Debug methodology to accelerate SOC timing convergence
TimeMonday, July 11th10:45am - 11am PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Topics
Back-End Design
DescriptionWithout a comprehensive methodology, Generic timing checks block ~40-50 % bandwidth of an STA engineer which can be better utilized for actual debug of the issues .

The Proposed solution Integrates the intelligence of a timing engineer into the signoff tool itself for analysis & debug . In simpler terms, the solution provides signoff tool with the brain of a timing engineer for Advance Comprehensive debug (Ad-Code)

It has 3 Segments for Now - TimingDebug, ClockQuality and ConstraintsSanity . Each one is a tool in itself .
Each sub-tool dumps reports, Identify issues and adds comprehensive debug (comments)
Furthermore, reports are co-related across corners and compared with the previous database.

There is a sub-tool for ECO’s also called SlackPenalty which generates ECO’s based on the design quality.