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Presentation

I/O Constraints Optimization
TimeMonday, July 11th11:45am - 12pm PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Topics
Back-End Design
DescriptionComplex hierarchical designs with stringent timelines require high quality constraints for predictable execution for partitions.

IO Constraint definition is one of the most challenging aspect for full chip timing convergence.

Current solutions from EDA tool vendors for budgeting is very iterative and not predictable.

Each iteration for partitions will take ~2-3 weeks which impacts the overall timing convergence

A new methodology is proposed using ML capabilities to achieve good quality IO constraints from the early stages, which can reduce the turnaround time significantly