Implementing QDI Design with Conventional Synchronous Design Flow: A Case of Long Distance Interconnect across Voltage Domain
TimeMonday, July 11th2pm - 2:15pm PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Back-End Design
DescriptionModern SoC design has been designed with clock-synchronous basis and it includes many sub-modules equipped with different clock domains. In SoC with GALS system, it is important to transfer payload across different clock domains. However, determining the number of register slices to highest frequency can make latency low due to more register slices at design time. In SoC including DVFS feature, implementation about voltage-crossing STA can be significant burden. Based on the observations, Quasi-Delay-Insensitive (QDI) circuits can become one of solutions to resolve these challenges. QDI circuits are asynchronous design without clock or global control signal. Its characteristics such as process variation robustness, clock-less can be exploited for long wire interconnect.
We propose that implementing QDI design with conventional synchronous design flow in long wire interconnect design across voltage domain. Proposed design is implemented leveraging synchronous design methodology and does not need to meet voltage crossing STA due to clock-less data transmission. Moreover, proposed design using only standard cell does not have burden of process node migration as against custom cell. As a result, we found all delay constraints for each module in the architecture and functionalities for whole DVFS levels are validated with only normal PVT condition.