On-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis using STA native timing engine
TimeTuesday, July 12th11:15am - 11:30am PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Back-End Design
DescriptionThe unified on-chip level power supply noise induced jitter analysis method is presented. The dynamic voltage drop simulation using vectorless scenario is performed. Cycle based jitter calculation was performed using STA native timing engine with interpolation method from different voltage libraries of same cell. The proposed method is integrated with dynamic voltage drop analysis and STA-based jitter calculation in a single flow. The results show that 76%~92% runtime reduction, 17%~29% less memory usage, 1ps accuracy with respect to spice simulation.