Experimental Validation of a Novel Methodology for Electromigration Assessment in On-chip Power Grids
TimeTuesday, July 12th10:45am - 11:00am PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Back-End Design
DescriptionA new methodology for assessment of the electromigration induced IR-drop degradation in on-chip power/ground grids has been validated by measurements performed on real silicon. A voltage tapping technique was employed for measurement of voltage variations at the power net, stressed with the constant source current at an elevated temperature. A voltage-drop between cathode and anode pads exceeding a specified threshold was considered as a failure. Times-to-failure were measured on a number of packaged test-grids and used for computing the mean-time-to-failure. The EM-induced voltage degradation in this grid was also analyzed with an assessment methodology based on a simulation of stress evolution everywhere in the grid, resulting in a voiding in some of grid branches and corresponding resistance increase. The stochastic nature of the EM was captured by introducing random distributions of atomic diffusivities and critical stresses across the grid and iterating them with Monte Carlo loops. A good fit between the measured voltage evolution kinetics at different grid nodes and that predicted by simulation, and the good agreement between measured and simulated failure distributions can be considered as the ever first experimental validation of this EM assessment methodology for on-chip power/ground grids.