Prototyping and verification of Power Delivery network for a Foveros 3DIC design.
TimeTuesday, July 12th10:30am - 10:45am PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Back-End Design
DescriptionImplementation of a robust power delivery network (PDN) is an inherent challenge of Foveros based 3D IC SoCs. With complex interdependency of the various 3DIC PDN components (Through Silicon Vias, C4 bumps, die to die microbumps, power grid pattern) across multiple dies, minor changes directly impacts power, performance and area (PPA) and affects design schedule. This work presents how an early prototype of 3DIC PDN ensures predictable design closure while meeting PPA metrics. Indigenous methods were developed using industry standard tools to bring in the 3DIC PDN components from multiple stacked dies into a single framework enabling designers to design, visualize, analyze and verify PDN prototypes. Early prototyping of the 3DIC PDN is necessary to enable independent design of the multiple stacked dies without any resets, ensure the Vmin targets are honored and ensure multiple instantiated (MI) cores see similar PDN. The model is scalable and can be built and verified across multiple DIE configurations and process nodes.