Presentation

DescriptionIn synchronous serial communication, clock frequency decides speed of design which is limited by Clock to Data Turnaround Time (tsco) or loop delay. Different design optimization techniques are used to minimize loop delay. Incorporating the core logic as part of IO buffer is one of them, which improves loop delay. Currently existing methodology is fully matured to deal with pure combinational or sequential design elements. In Improved System level integrated IO interface (SLIO) full custom design, both sequential and combinational elements are integrated together and needs both combinational timing constraints (rise-fall delay and transition) and sequential constraints (setup-hold, clock-to-q delay). In this paper, all characterization challenges due to improved SLIO design are discussed. New effective methodology is proposed for all the characterization challenges and thus enabling the accurate timing signoff at SOC level.