Pushing Boundaries - Challenges for Next-Generation Chip Design
TimeWednesday, July 13th3:30pm - 5pm PDT
Location2008, Level 2
Event Type
Back-End Design
Engineering Tracks
Back-End Design
DescriptionAdvanced technology nodes such as 5nm and 3nm, 2.5D/3D stacking, MCMs, and design size - all pose unique challenges for EDA tools, design methodologies, integration, and testing. This session show cases real-world challenges and solutions for next-generation high-performance chip design and test in both 2.xD and 3D. Talks feature leading-edge back-end design flows, disaggregated product architecture methodologies, and test solutions for high bandwidth memories.