Design Verification for Virtual Prototype Exploiting UVM
TimeMonday, July 11th11:15am - 11:30am PDT
Location2012, Level 2
Event Type
Embedded Systems and Software
Engineering Tracks
Embedded Systems
DescriptionIn the conventional development process of the embedded system, SW development is strongly dependent on the HW prototype. SW development often encounters an embarrassing situation due to the lack of FPGA resources and its slow performance. Virtual Prototype can help the shift-left of SW development significantly. There is no worry about FPGA resources, but the functional accuracy compared to HW design must be improved enough to be utilized in the SW development step. In this work, we propose a verification method for a virtual prototype exploiting the UVM environment which is already prepared for the RTL verification. The proposed method translates the UVM test vectors into the TLM payloads regardless of the HW interface and also supports the asynchronous inter-process communication to thoroughly update the scoreboard of the UVM-side. The practical use case demonstrates that the custom-designed virtual prototype is well verified and its functional accuracy achieves the same level as RTL design, which means it is sufficient for use in the SW development step.