Rapid Embedded Software Verification Through Hardware-Accelerated, Parallel SystemC TLM Simulation - A RISC-V Example
TimeMonday, July 11th11am - 11:15am PDT
Location2012, Level 2
Event Type
Embedded Systems and Software
Engineering Tracks
Embedded Systems
DescriptionToday’s complex HW/SW systems require functional target software verification as early as possible in the design cycle to meet tight release schedules. Full-system-simulators, so called Virtual Platforms (VPs), built on the SystemC TLM-2.0 standard are the go-to tool for this job. However, due to increasing target system complexity, construction of high-performance VPs for interactive use is posing a growing challenge.

In this work we demonstrate how VP performance can be increased using our parallel, hardware-accelerated SystemC TLM-2.0 simulation technology. We present speedups of 3.6x for compute intensive workloads in our RISC-V case study. In addition, we exhibit the capabilities of our technology in a representative, interactive demonstration.