A Dynamic approach towards NOC Performance Verification in Pre-Silicon and Overcome the traditional Overheads
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionPerformance is the most important source of competitive advantage for modern SOCs and NOC is the one of the most important backbones of the SOCs which helps to accomplish that. The performance verification of the NOC is the very significant on top of the functionality. Since there are diverse ways of configuring the SOCs – different IP and interconnect topologies, number of masters and slaves, bus widths, packet sizes, clock speeds, enabling performance verification early during the design cycle and scaling it up to different levels for environment gets overwhelming. To achieve the multiple level of performance verification in an SOC, there is a persistent need for novel approach for performance analysis and debug during earlier design cycle.
The proposed solution is using the AMBA VIPs and third-party Performance Analyzer for automated protocol performance analysis and debug. This verification methodology has provided enormous gain in multiple levels of NOC performance verification in an SOC and from the first test case itself we are able to start on the performance analysis. This approach has enabled us to provide meaning performance analysis data to the design and architecture team, fixed the design issues, NOC generation tool issues and able to achieve the expected performance in the silicon.