A scalable framework to validate interconnect-based firewalls to enhance SoC security coverage
TimeWednesday, July 13th4:30pm - 4:40pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
DescriptionEmerging technologies have an enormous capacity to enrich our lives and change the world. But those technologies must be built on a strong foundation of security and trust. Securing technology products is one of the industry’s most pressing and challenging goals. Hence ensuring these new security technologies do not pose any risk is a competitive task. As a system validator one must analyze and predict all possible attack scenarios for the product. An area that is extremely critical to validate is access control-based hardware security features. Current SoCs implement NoC based firewall design architecture to overcome these security vulnerabilities. But the design itself is so complex that there are a lot of possible permutations and combinations to be validated and it becomes a bottleneck for security verification. To achieve hundred percent security coverage there is dire need to develop a scalable validation framework.
The proposed solution is the first of its kind, built from scratch to address the above shortcomings. The automated framework is scalable across multiple validation platforms. It has enabled quicker turn-around time to develop tests, detection of quality hardware bugs thereby increasing the security robustness of the product.