TCP/IP Hardware Stack Design and Verification Challenges
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionThe offloading of TCP/IP in hardware is a popular option for addressing the reliable and low-latency requirements of modern high-speed networks. This protocol offers a connection-oriented communication that guarantees the data delivery through data acknowledgments and retransmissions, while also implementing flow control and congestion control mechanisms. Because of its complexity, the verification of the protocol poses many challenges, since off-the-shelf verification IPs do not exist, whereas connecting high-level models and including quality metrics is not straightforward.
This work presents a hardware architecture for fully offloading the TCP/IP protocol and addresses the verification challenges of such a complex design by introducing a UVM-based testbench. Its core is a software model of the protocol as well as different types of sequences for generating random and directed tests. The structure is highly configurable and extensible to target every functionality of the design and the underlying protocols of the stack, while incorporating quality metrics that guarantee the full coverage. The efficient design monitoring offers a systematic methodology for tracking the verification process and achieves the functional verification of the whole TCP/IP stack including all communication protocols.