A unified IP QA methodology to improve validation coverage and throughput
TimeMonday, July 11th5:20pm - 5:30pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Event Type
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionDesign IP has helped drive innovation of IC and system-on-chip (SoC) designs by modularizing design components and enabling re-usability. As usage of IP increases, so does the challenge of building a quality assurance (QA) framework that understands and provides effective validation coverage for IP production and integration workflows.

An effective IP QA methodology requires coverage over a wide spectrum of design views and formats in IP flows, such as functional, physical, electrical, and other views. In addition, it must also handle non-uniformity between different sources and integration targets for IP components such as new categories of IP, or divergences in process technology for different applications.

Our paper discusses the steps of planning and implementing an IP QA methodology based on Solido Crosscheck and ST CAD Infrastructure, that handles the depth of knowledge required for different design views, as well as the flexibility for handling different IP types and use cases. We will also show examples of potential issues addressed by this framework, and how it improves overall IP quality metrics and production schedules.