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Presentation

A Novel Duty-Cycle Adjuster Circuit , To Be Used As Part Of Automatic Clock Duty-Cycle Corrector Circuit
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionClock Duty Cycle Corrector circuit is a critical component of any Double Data-Rate applications , like HBM IO etc. , in order to maintain proper timing margin for both positive & negative edge sampling . Existing digital control based DCC architectures need training algorithm & RTL-coding . In existing analog DCC designs , there are limitations like limited duty correction , poor controllability of DCA o/p signal bias level etc.

In our DCA(Duty Cycle Adjuster) design , as part of DCC circuit , we claim to get rid of training algorithm & limitations of existing analog DCC circuits .