Presentation

DescriptionPaper details the methodology and implementation for electrical characterization, EDA CAD View generation, IP packaging and validating all the CAD Content required for IP Integration in SoC. This solution is technology agnostic and supports ~50 EDA/CAD views (functional models, Electrical models, physical models, DFT/test models) that are required to run supported SoC implementation flows and tools. Fully automated solution requires minimal user input and reduces the manual effort of IP CAD View Generation and Validation and improves the cycle time of the activity by 58%. This solution is currently deployed for Analog Mixed Signal IPs and has the capability to support specific Memories and Periphery IP. Using this solution ~300 IPs across 27 technology nodes has been enabling ~44 active SoC in a year.