Formal Verification of Deep Neural Networks in Hardware
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionDeep neural network (DNN) verification is an emerging field. The problem is more pronounced when they are modelled as hardware logic. Existing formal verification solutions for such hardware designs are fraught with issues like scalability and compute intensive resources. We solve this problem by creating a lightweight verification infrastructure and verifying the DNN logic by way of equivalence check. The light weight formal verification model is created by applying neural network simplification approaches discussed in the presentation. The DNN formal model as a consequence is made simpler by removing the unwanted nodes, as a result it is capable of verifying intricate deep neural network designs effectively as compared with simulation based conventional strategies. The approach is applied on a design which is a car collision avoidance system (CARCAS) which is a logic deployed in autonomous car driving paradigm.