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Presentation

Smart Strategy to analyze CDC Violation related to IPs Interaction at SoC
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionAs the complexity of memory controller increases, the challenges for integration of standard IPs in controller
associated with multiple clock domains proportionately increases. One very common issue observed at SoC
abstraction is handling of large violation set spread across multiple IPs used in design and few arise by IPs interaction.
The most common flow to handle such complex SoC is to follow bottom-up hierarchical approach. Now bottom up
hierarchical approach can be exercised in two ways, one using blackbox technique where lower blocks are abstracted
with boundary constraints and integrated at SoC TOP with blackbox block. This approach gives lot of issues breaks
the constant and clock propagation happening through the block boundary input to output, plus demands strictly
reliable boundary constraints and hard to debug when any crossing is originated by boundary if its real or not. All
these issues can be overcome by preserving the boundary sequential elements and combinational logic which is
directly connecting input to output of block. This is called metadata which is integrated at higher abstraction level
smoothly without too much reliability on constraints and gives effective crossing set. This approach also helps in
surfacing potential real reconvergence issue whose synchronizers are lying deep inside the lower abstracted blocks.
Although signing off CDC requires precise design knowledge but bottom up hierarchical approach reduces the
violations quantum effectively which are local to IPs itself. Therefore SoC engineer can effectively focus on IP
interaction issues. Are we done with the effective violation set analysis for sign off, NOT yet! After taking this key
hierarchical flow step, rest of the violation still may sounds undesired due to architectural assumptions. In this paper,
we will discuss few more ways on top of the hierarchical approach to weed out unwanted violations at SoC CDC sign
off –
1. Isolation cells between IPs: Two IPs interacting which are in two different power domains, hence isolation
cell inserted between them. This isolation cell gives lot of new CDC paths from one IP to another IP. However
due to ensured power sequence, clocks to IPs will be stopped before isolation enabled toggles and restores
after switching operation. Therefore all the crossing paths going through such identified isolation cells are
unwanted. Similarly, reconvergence of IPs internal synchronizers at SoC TOP may be unwanted when IP is
itself in power off domains i.e. functionally not excited.
2. Multiplexed PADs cells: Due to design needs, usage of PADs is limited. So it is required to multiplex input
and output through inout PADs. Now GPIO PADs as end points are always asynchronous in nature forming
CDC end/start point and multiplexing may give rise to unwanted crossing paths form one IP to another IP.
3. Protocols handling Crossings: There are certain protocols present at SoC top between IPs whose interaction
is having standard protocol which ensures the NO requirement of synchronization. Say four frames are
received by receiving IP, one SOP, two payloads and one EOP. The detection of the end of protocol requires
interrupt which we need to synchronize. So received payload will be only read after the end of interrupt is
acknowledged. Therefore no need to synchronize the payload and fine to consider stable until interrupt is
not acknowledged.
4. No reset synchronization: one, gating the system clock until reset is de-asserted. So violations based on
clocks that is gated during reset becomes unwanted from central reset handler unit to IPs. Second, there
will be no functional issue when reset de-asserts and clock is some event generating logic because it is
intended that software will read the value captured at flop's output and then clear the output. However, it
must be ensured that the duration of this reset is such that in between successive reads, output of flops is
cleared. Therefore, such software reading doesn't require reset to be synchronized.

Hence, with mentioned add-on SoC know-how over the hierarchical approach we are able to handle IPs interaction
at SoC effectively.