Presentation
Improving FPGA Quality & Prototyping Turn Around Time Using Static Verification
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionFPGA designers manually modify their designs to meet FPGA requirements such as inserting BUFGs, changing memory macros, and I/O pads etc. which can lead to introduction of design issues
Some of these issues are found very late in prototyping flow and at times not easy to debug, leading to increased iterations and TAT for closure
- Functional failures caused by bad coding styles like multiple driver issues, combinational loops, etc.
- Logic getting optimized due to hanging or unconnected logic
- Overriding assignment issues caused by incorrect breaking across XMRs using force commands
- CDC metastability and re-convergence issues caused by incorrect partitioning across CDC synchronizers, etc.
Some of these issues are interpreted differently in prototyping flow for which user needs to be cautioned
- Multiple driver issues caused by incorrect crossing module reference (XMR) with assign commands
- Overriding assignment issues caused by incorrect breaking across XMRs using force commands
Using Static Verification (specific rules) prior to running Prototyping can not only improve the FPGA quality but also reduce the number of iterations and turnaround time in Prototyping
Some of these issues are found very late in prototyping flow and at times not easy to debug, leading to increased iterations and TAT for closure
- Functional failures caused by bad coding styles like multiple driver issues, combinational loops, etc.
- Logic getting optimized due to hanging or unconnected logic
- Overriding assignment issues caused by incorrect breaking across XMRs using force commands
- CDC metastability and re-convergence issues caused by incorrect partitioning across CDC synchronizers, etc.
Some of these issues are interpreted differently in prototyping flow for which user needs to be cautioned
- Multiple driver issues caused by incorrect crossing module reference (XMR) with assign commands
- Overriding assignment issues caused by incorrect breaking across XMRs using force commands
Using Static Verification (specific rules) prior to running Prototyping can not only improve the FPGA quality but also reduce the number of iterations and turnaround time in Prototyping