Learnings from RDC Sign-Off on Low Power SoC
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionReset Domain Crossing (RDC) sign-off is a big challenge to handle thousands of violations in large chip design integrating IPs. Low Power SoC has software resets as well as power related resets from low power management techniques. Interactions between increased resets demand new verification method to avoid meta-stability, glitch, and re-convergence issues for resets. Hence, there is need to address RDC issues efficiently by reducing noise violations on early RTL design stage. In this paper, we present solutions for RDC sign-off on Low Power SoC. It presents how CDC setup flow can be leveraged for getting started on RDC analysis. After that, strategies are introduced to identify reset domains considering power domains. Reset sources were categorized into several reset groups: power related resets for each power domain and software resets inside complex modules, which some of them were abstracted or not. Additional false path constraints were defined considering power gating sequences. These techniques reduced RDC paths from thousands to a few relevant paths up to 85.8%. The paths were mostly special protocol paths which definitely needed the designer's scrutiny before sign-off. This paper demonstrates usage of these strategies on our design where whole reset domain crossing issues are signed off.