CDC Signoff Flow with DFT Logic
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionIncreasing complexity of SoC designs and variety of asynchronous clocks introduces new challenges for validation of designs from clock domain crossing (CDC) perspective. Such verification is traditionally performed at RTL level. DFT insertion which affects clocks distribution schemes and data paths even further complicates CDC analysis.
This paper illustrates systematic flow performing verification twice, once at RTL level, next at the design with inserted DFT solution. The flow makes debugging violations easier, especially as different engineers handle design at the mentioned stages. The established CDC verification approach provides greater confidence on silicon results and can be integrated into any SoC design flow.