Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors
TimeWednesday, July 13th5pm - 5:10pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
DAC Pavilion Gladiator Arena Poster Battle
Engineering Track Poster
DescriptionMost recently in the space of Hardware Assisted AI, there has been AI infused high performance micro- processors which have been announced. The design of these high performance microprocessors with inline accelerators need extensive tradeoff analysis during the various stages of the design, and a comprehensive validation process that is done on systems assembled with different versions of manufactured chips as they come from the foundry. In this paper we describe how pre and post silicon analysis play a role in the design and validation of a high performance micro-processor with embedded AI accelerators. We introduce a comprehensive pre-silicon analysis framework that consists of various tools that help assess the power-performance trade-offs, and present how this framework is used in analyzing the impact of inline AI accelerators during design phase. We also present a post-silicon analysis infrastructure that ties in with the pre-silicon framework. We discuss how this end-to-end process was used in the design of an AI infused high performance micro-processor, touching on benchmarks, hardware bring up and model-to-hardware correlation.