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Presentation

SYSTEM-LEVEL DEADLOCK SIGN-OFF USING ARCHITECTURAL FORMAL VERIFICATION
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionWhile formal verification is growing and proven to be very impactful in identifying deadlock issues in the design, due to proof complexity at system level, traditional constraint based random verification methodology continued to be used for identifying such issues and sign-off. To address this problem, we leveraged architectural formal verification methodology to reduce the proof complexity and enabled the use of formal verification for system-level deadlock verification.
We will use a case study of a hardware based lossless Compression IP - a complex networking accelerator IP, as a system and show how the proposed method was applied including decomposition and mapping of complex system to small block level properties.