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Presentation

New Methodology for Extracting Test Coverage on Pure DRAM & Flash Design
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionMemory design such as DRAM & Flash has made by custom design methodology, known as TR-level design. To detect the fault of cell, core and logic part of memory, they have made the function test program based on the knowledge and know-how by themselves. When it comes to manufacturing defect, even though they haven’t known numerically how much they are covered through their program, it is worth for memory business until now. However, we try to measure the test coverage numerically to guarantee the quality of memory product as the process and design are getting complicated. We have faced on several big problems that there are no experiences and confidential tools about over 60 million faults on pure DRAM/Flash that have transistor, switch and asynchronous design. We end up obtaining the test coverage of memory product and it is the first step for big custom design like memory. This paper will show you something important about how you deal with the memory design for obtaining test coverage without scan DFT.