Fast Design Space Exploration using RTL Architect for DRAM Designs
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionFinding optimized design architecture is a main issue for circuit design under specific design conditions because there are tradeoffs to be considered between design constraints like area, performance and interconnection complexity. To evaluate design constraints, prototyping methods are used. Optimizing DRAM peripheral circuits is very challenging due to few metal layers, unbalanced aspect ratio and tight chip area constraint and it makes difficult to predict whether the design satisfies target specification or not before layout implementation. The conventional RTL-to-GDSII approach is too time-consuming for prototyping. This work used RTL Architect as a rapid prototyping tool for DRAM designs and decided optimization strategy of sub-block. RTL Architect enables to predict the implementation results of various candidate designs. The accuracy of PPA estimated by RTL Architect is sufficient to decide which is the best design among the candidates.