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Presentation

ProtoLint: Protocol- and IP-Aware Lint for RTL Integration
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionLarge scale SoC requires RTL integration step in each subsystem level. The task is to connect IP ports and many of them are part of standard interfaces such as AXI and APB. RTL integration contains lots of pitfalls which are prone to human errors. According to our verification statistics, more than 20% of bugs in SoC implementation were caused by wrong RTL integration. Lint, static code analysis tool, is widely used to detect erroneous RTL integration; however, checking only with general RTL rules misses large space of serious connection bugs since it is not aware of the meaning of a port in an interface protocol. For example, zero-tying QREQn port of Q-channel interface will make the IP stuck at its idle state. The RTL-only lint tool will ignore this connection or raise low severity warning for the tying which tends to be ignored by integration engineers. We propose ProtoLint to tackle this problem. By utilizing the protocol and IP-specific information, ProtoLint can detect many critical connection bugs which cannot be detected by the RTL-only lint tool. By retrospectively applying ProtoLint to the two past projects, ProtoLint could detect tens of critical bugs in less than 5 minutes which had been detected over 17 to 18 weeks by simulation-based verification during the projects.