Shift Left DFT Sign-off Methodology for Edge AI Processor
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionWith the increasing edge AI compute requirements at the Internet of Things (IoT) endpoints such as virtual assistants, the semiconductor world is racing to develop high performance AI-specific chips. Such designs possess replicated cores and distributed memories. One such design with distinguished architecture is the ARA-2 processor, designed with the goal of solving edge applications where requirements span high compute, model flexibility and energy efficiency.
This complex architecture has challenging DFT needs for several reasons. One reason is that DFT logic is inserted at RTL, so from a DFT standpoint, it is critical to make correct design decisions early. Faster time-to-market requires faster design turnaround time (TAT), hence iterations back to RTL in the design flow should be minimized by checking readiness of the RTL for DFT logic insertion early and effectively. ATPG occurs too late in the design process and debug for any coverage hole at ATPG is hard and expensive and impacts TAT, so it is more efficient to do fault coverage analysis at RTL stage. The design after synthesis will not be full-scan, and various parts of the design will be hard to test due to excessive sequential depth produced by flip-flops that will not be scan-inserted at synthesis (i.e. non-scan), and paths between memory arrays or from memory arrays to flip flops. Therefore, finding these areas early during design would be beneficial.
In this paper a part of methodology is illustrated comprising the Design Rule Checks (DRCs) and fault coverage analysis used for ARA-2 AI processor. Along with it, the paper will discuss the DFT issues that can be discovered at RTL and fixes to such issues performed at RTL, and coverage holes due to future netlist connectivity that need to be addressed at RTL for effective correlation between RTL and netlist.
In the end, paper summarizes the results in coverage and proves how such methodology is able to manage the scan readiness of AI chip.