Dynamic CDC Verification with Enhanced Jitter Modeling in Synchronizers
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionOver the past decade, the move to System-on-Chip (SoC) design has dramatically increased chip sizes.
Typical SoC designs today are big enough to stress the capacity of state-of-art verification flows. More importantly, they have many subcomponents with complex interactions. Many asynchronous interfaces exist between the processor cores, caches, application engines, integrated memories, system, and networking interfaces. Each subcomponent usually has its clock domain. These independently developed components enable a rich feature set for the SoC. However, accompanying this abundance of features, there is a proliferation of internal and external protocols and aggressive power requirements that leads to an explosion in the number of asynchronous clocks in SoCs. Ensuring that this complex SoC works according to specifications demands that design and verification teams spend increasing time verifying the correctness of asynchronous boundaries on the chip.
Metastability on CDC paths can lead to unpredictable results and delays. In order to mitigate the risk of metastability, synchronizers are instantiated in the design. However, these synchronizers can cause secondary-level problems like correlation loss. Traditionally structural analysis has been used to signoff. Nevertheless, structural analysis has some inherent limitations. As a result, problems like the functional impact of reconvergences and signal skew on synchronizer paths can not be detected. This paper presents a robust signoff methodology that works in conjunction with structural analysis and identifies the problems where structural analysis is insufficient.