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Presentation

Left Shift of Multi-Cycle Paths and False Paths Signoff By Formal and Dynamic Simulation Methodologies with significant ROI
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionToday’s mammoth chips have breached the milestone of 100 billion transistors as there is constant endeavor to pack more transistors in the limited real estate possible in complex devices clocking around 45 billion operations per second. Design and verification methodologies coupled with EDA tools play a major role in making sure the complex designs meet the expected numbers of Power, Performance and Area and reaching market on time without bugs. Left shifting traditional constraint validation to RTL enables to catch issues much earlier in the design cycle. Constraint validation is quicker in the RTL stage and so is fixing. We explored the approach of validating the Multi-Cycle Paths and False paths in RTL formally and by dynamic simulations. In our IP we found out around 20% of the constraints could be evaluated formally and remaining had to be evaluated by dynamic simulations. We were able to validate the constraints and find out wrong MCP scenario resulting in cleaning up the constraints. The timing closure is speed up by around 5%. Left shift achieved here is small but significant as same methodology when scaled up to bigger blocks like subsystems or SoCs with considerably higher number of constraints, considerable left shift can be achieved. Most importantly this will help to improve the time-to-marked of the chip with improved quality.