Low Power Verification Challenges of Hierarchical UPF in Discrete Graphics SoC Design
TimeTuesday, July 12th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Engineering Track Poster
DescriptionPower management has turned up into a critical requirement at System on Chip level. Just as the complexity of an SoC demands a well-structured hierarchical approach to design and verification of its functional specification, the complexity of the power management infrastructure for an SoC requires a hierarchical methodology that enables separation of concerns and supports partitioning, parallel development, and reuse. In this paper, we have proposed guidelines/strategies which we should follow while using hierarchical UPF. This approach has an advantage of reusing IP design UPF at SoC level and same UPF can be used for Front End or Structural Design flows. The single UPF usage across Front End validation and Structural implementation addresses a common verification platform and reduces silicon bug. This has increased turnaround time by 60% required for power implementation at SoC level and ensured reliable results from a low power design and verification flow. We have described the challenges we faced while integrating IP specific power intent to SoC level, tool limitations and suggested guidelines which we should follow while working on the hierarchical UPF methodology. The proposed methodology is illustrated in the context of discrete graphics design architecture that was used to validate the concepts.