Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionAdvanced markets like IOT, and embedded consumer, industrial and automotive drive complex power managed system design with integrated mixed-signal, RF and power management contents.

Designs with large number of applications with lowest power consumption and on time delivery are the key contributors in winning the market. While technology scaling enables more complex functionality on SoCs, power consumption increases significantly and mandates the reduction of active and standby power. Battery powered SoCs require considerably more aggressive power reduction techniques. To address these challenges, we need advanced low power techniques seamlessly supported at IP and system specification, design, integration, verification and sign-off stages for both custom and semi-custom design contents.

These SoCs have large number of soft, hard and mixed-signal IPs with power reduction techniques such as power gating, voltage domains and clock gating implemented at both IP and SoC levels. In addition to SoC power management (PM) complexity increases as the need for state retention in the presence of power gating for several IPs to meet system level performance challenges. To achieve entitled power with such complex and advanced design techniques, conventional verification methodology proves to be inefficient and require power aware (PA) verification at both RTL and GL stages. Conventionally the verification framework involves initial non-power aware (PA) RTL based functionally focused verification, followed by PA RTL verification for a sub-set of test suite focusing only on power management scenarios. After the design implementation following synthesis, PA GL simulation is performed for limited test suite without timing annotation. Finally, full regression is performed with non-PA GL netlist with timing annotation across corners.

This paper presents identified bottlenecks in conventional verification flow, and how the same is overcome by optimizing the flow to have a more efficient verification framework with limited flavours thus achieving both higher quality and early design closure with limited overheads. The proposed methodology is applied on an industrial design execution of a power managed, mixed-signal, embedded processing SoC. The results from the execution is presented to highlight the quality and efficiency improvements achieved.