Efficient stimulus generation techniques for a UVM TB
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionUVM has standardized most of the functional verification process (creation of a Test bench(TB) components), but stimulus generation is at least partly left to the expertise of the engineer.
UVM documentation (user guides etc.) give a good introduction on creating stimulus (virtual sequences etc) , but don’t do a good job of explaining complex stimulus generation scenarios.
Stimulus generation typically involves following aspects of the verification environment:
Sequences, Constraints, Tests

We tried to demonstrate a few complex stimulus generation scenarios that are not obvious from the UVM documentation, using various techniques like ‘layered constraints’, ‘usage of strategy design pattern in test coding’ and ‘coordinated random traffic generation’. We also tried techniques like reactive stimulus generation streaming sequences , pro-active master sequences , policy based layered constraints coding for a TB being developed from scratch[3] and could benefit immensely in achieving faster verification closure and urge the DV engineers to try these techniques.