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Presentation

Pre-Silicon Design Quality and Test Readiness through Efficient Verification Methodology
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionAdvanced markets like IOT, and embedded consumer, industrial and automotive drive complex power managed system design with integrated mixed-signal, RF and power management contents.

Designs with large number of applications with lowest power consumption and on time delivery are the key contributors in winning the market. Post silicon test and validation of such a complex SoC though a critical process towards readiness for customer release, involves significant effort and cycle time. Conventionally test hardware and test procedure development mature pretty late in the produce development cycle, most of the times much later than the actual IC fabrication and thus impacting the time-to-market.

Analog mixed-signal, power management and RF integration adds much to the complexity of the post fabrication IC test procedures.

This presentation describes a solution to enable much earlier maturity of test procedure readiness by benefiting from the pre-silicon verification as a vehicle. Further the goal is to minimize the necessity of analog mixed-signal (AMS) co-simulation in aspects like analog test bus (ATB) verification and trim sequence verification. With advanced analog modelling techniques such tasks could be easily performed in digital mixed-signal (DMS) co-simulations reducing significant amount of of design verification (DV) cycle time. Performing such tasks in DMS further provides a channel for test firmware (TFW) verification all of which can contribute to faster silicon bring up and the solution as a whole is a vehicle for pre-silicon test readiness. The paper also highlights the results from application of this methodology to an industrial mixed-signal power managed embedded processing SoC.