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Presentation

Robust FSM Verification Approach Handling Critical CDC Convergence Scenarios
TimeMonday, July 11th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Topics
AI
Back-End Design
Cloud
Embedded Systems
Front-End Design
IP
DescriptionThe Finite State Machines (FSMs) coupled with Clock Domain Crossing (CDC) is one of the challenging aspects in Verification. Metastability in the system due to CDC causes vulnerability in FSM decoding and the effect is catastrophic. This paper describes the methodology using Formal Verification techniques and tools to efficiently verify the design with complex FSMs and involving CDC. Our methodology also addresses many fundamental challenges in the Simulation based Verification.