Diagnosis of Faults by Fault Simulation on PCIe
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionModel based fault injection can be used to measure the quantity of faults within a design that:

· May cause the failure of a device such that it violates a safety goal

· The ability of the safety mechanism(s) to correct, react, or signal the violation of a safety goal

Faults are injected and the results of the simulation are specific to the design provided.

A good fault model duplicates real-life defects such that when faults are detected by a test in simulation, the test will also detect defective parts in production. Real-life defects are caused by many environmental and aging factors, and can include shorts to power, ground & transistors, open transistors, bridged and open interconnects. Defects cause a variety of unintended physical and simulated behavior. Some defects cause the combinational logic to behave as latches, timing of the circuit to change, cause oscillations; some stop logic from changing state.

This Presentation uses Fault Simulation techniques to demonstrate how 99+% of fault of limited PCIe modules may be detected and given Fault Status for analysis of the design acceptance for manufacturing. The technique used is auto injection with standard fault format (SFF) and detection using tool from EDA vendor.