AI assisted smart analysis (AISA) for system level issue localization in post silicon validation
TimeWednesday, July 13th5pm - 6pm PDT
LocationLevel 2 Exhibit Hall
Event Type
Engineering Track Poster
Engineering Tracks
Back-End Design
Embedded Systems
Front-End Design
DescriptionThis paper would propose a method, aiming at creating an Artificial Intelligence (AI) based solution using Machine Learning (ML) techniques, to expedite debug and localization of source of issues seen in system level post silicon validation executions.
The debug challenges usually are inversely proportional to the controllability and observability at any phase of design validation, may it be pre-silicon or post-silicon. The challenges intensify during post silicon phase as the liberty to reach at signal or register level becomes limited when execution happens on real HW with silicon. In general, during the beginning phases of post silicon validation the focus is majorly towards finding HW bugs and fixing as early as possible through workarounds or silicon re-spins if necessary, to minimize the cost of HW fixes at later stages where the loss incurred may be humongous. There are number of solutions proposed and practiced in industry today to address challenges in HW bug localization e.g., Design for Debug entities, scan chains, JTAG, Trace buffers, etc. There is a considerable amount of research that has happened around HW bug localization in post silicon but those are not in the scope of this paper to discuss.

As the product nears the customers, the debug capabilities in HW/SW/FW are further diminished due to power, area, performance, cost, and security implications. The proposal at present targets the system level debug challenges in post silicon validation of a product when the individual IPs of SoC have been through component level validation, integrated with the system from HW, SW and FW perspective and are now under validation as nearly the end product solution. To further narrow down, this paper discusses the proposed solution of “source of issue” localization at system level in conjunction with functionality issues countered in peripheral IP solutions.

Post silicon debug challenges for Thunderbolt4 or USB4 IP at system level are taken as reference and the proposed AI & ML based method is discussed. Given consideration and opportunity, this method may even extend to other areas of post silicon validation and debug challenges and can help accelerate time to market.